公开(公告)号：US20230197586A1

公开(公告)日：2023-06-22

申请号：US18084604

申请日：2022-12-20

Applicant: Infineon Technologies AG

Inventor： Chan Lam Cha ,  Wern Ken Daryl Wee ,  Hoe Jian Chong ,  Chin Kee Leow

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/49575 ,  H01L21/56 ,  H01L24/20 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/211

Abstract: A chip package includes a chip with at least one contact pad, a contact structure formed from at least one continuous longitudinally extended electrically conductive element by attaching the conductive element to the contact pad in at least three contact positions, wherein the conductive element bends away from the contact pad between pairs of consecutive contact positions, and an encapsulation partially encapsulating the contact structure, wherein the encapsulation includes an outer surface facing away from the chip, and wherein the contact structure is partially exposed at the outer surface.

公开(公告)号：US11217511B2

公开(公告)日：2022-01-04

申请号：US16379405

申请日：2019-04-09

Applicant: Infineon Technologies AG

Inventor： Sock Chien Tey ,  Chan Lam Cha ,  Hoe Jian Chong ,  Cher Hau Danny Koh ,  Kim Guan Tan ,  Mei Yong Wang

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A packaged semiconductor device includes a carrier having a die attach surface, a semiconductor die mounted on the die attach surface and comprising first and second conductive terminals disposed on an upper side, a first clip that extends over the semiconductor die and is electrically connected to the first conductive terminal, a second clip that extends over the semiconductor die and is electrically connected to the second conductive terminal, and an electrically insulating encapsulant body that encapsulates the semiconductor die. An outer end of the first clip is exposed from the encapsulant body and provides a point of external electrical contact for the first conductive terminal. An outer end of the second clip is exposed from the same or a different side face of the encapsulant body as the first clip and provides a point of external electrical contact for the second conductive terminal.

公开(公告)号：US20190164873A1

公开(公告)日：2019-05-30

申请号：US15822745

申请日：2017-11-27

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Chan Lam Cha ,  Wei Han Koo ,  Andreas Kucher ,  Theng Chao Long

IPC: H01L23/495 ,  H03K17/687 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49575 ,  H01L21/4803 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49568 ,  H02M1/088 ,  H02P27/04 ,  H03K17/6871

Abstract: A semiconductor package includes a plurality of half bridge assemblies each including a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side. Each metal lead has a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead. The semiconductor package also includes a controller die configured to control the power transistor dies. Each power transistor die, each metal lead and the controller die are embedded in a mold compound. Bond wire connections are provided between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.

公开(公告)号：US12176222B2

公开(公告)日：2024-12-24

申请号：US17536538

申请日：2021-11-29

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Thorsten Meyer ,  Chan Lam Cha ,  Wern Ken Daryl Wee ,  Chee Hong Lee ,  Swee Kah Lee ,  Norliza Morban ,  Khay Chwan Andrew Saw

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/00 ,  H01L25/18

Abstract: A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.

公开(公告)号：US20230170226A1

公开(公告)日：2023-06-01

申请号：US17536538

申请日：2021-11-29

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Thorsten Meyer ,  Chan Lam Cha ,  Wern Ken Daryl Wee ,  Chee Hong Lee ,  Swee Kah Lee ,  Norliza Morban ,  Khay Chwan Andrew Saw

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/367 ,  H01L21/56 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L21/4853 ,  H01L23/31 ,  H01L23/49811 ,  H01L23/367 ,  H01L21/568 ,  H01L25/50 ,  H01L25/18

Abstract: A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.

公开(公告)号：US20210025774A1

公开(公告)日：2021-01-28

申请号：US16890461

申请日：2020-06-02

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Paul Armand Asentista Calo ,  Chan Lam Cha ,  Kok Yau Chua ,  Jo Ean Chye ,  Chee Hong Lee ,  Swee Kah Lee ,  Theng Chao Long ,  Jayaganasan Narayanasamy ,  Khay Chwan Saw

IPC: G01L9/00 ,  G01L19/14

Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.

公开(公告)号：US20200328140A1

公开(公告)日：2020-10-15

申请号：US16379405

申请日：2019-04-09

Applicant: Infineon Technologies AG

Inventor： Sock Chien Tey ,  Chan Lam Cha ,  Hoe Jian Chong ,  Cher Hau Danny Koh ,  Kim Guan Tan ,  Mei Yong Wang

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A packaged semiconductor device includes a carrier having a die attach surface, a semiconductor die mounted on the die attach surface and comprising first and second conductive terminals disposed on an upper side, a first clip that extends over the semiconductor die and is electrically connected to the first conductive terminal, a second clip that extends over the semiconductor die and is electrically connected to the second conductive terminal, and an electrically insulating encapsulant body that encapsulates the semiconductor die. An outer end of the first clip is exposed from the encapsulant body and provides a point of external electrical contact for the first conductive terminal. An outer end of the second clip is exposed from the same or a different side face of the encapsulant body as the first clip and provides a point of external electrical contact for the second conductive terminal.