公开(公告)号：US20200098617A1

公开(公告)日：2020-03-26

申请号：US16695999

申请日：2019-11-26

Applicant: Infineon Technologies AG

Inventor： Oliver Hellmund ,  Ingo Muri ,  Johannes Baumgartl ,  Iris Moder ,  Thomas Christian Neidhart ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/306 ,  H01L21/28 ,  H01L21/74 ,  H01L29/872 ,  H01L21/764 ,  H01L29/16 ,  H01L29/861

Abstract: A semiconductor device includes a first epitaxial layer, a second epitaxial layer disposed below the first epitaxial layer, a conductive layer disposed below and directly contacting the second epitaxial layer, and a plurality of spacers disposed between the second epitaxial layer and the conductive layer. The conductive layer includes a metal. The plurality of spacers include a bulk semiconductor material.

公开(公告)号：US20180277391A1

公开(公告)日：2018-09-27

申请号：US15927551

申请日：2018-03-21

Applicant: Infineon Technologies AG

Inventor： Iris Moder ,  Sophia Friedler ,  Ingo Muri ,  Hans-Joachim Schulze

IPC: H01L21/3213 ,  H01L29/10 ,  H01L29/739 ,  H01L29/66 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/324 ,  H01L21/784 ,  H01L21/304

CPC classification number: H01L21/32139 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/304 ,  H01L21/30608 ,  H01L21/3083 ,  H01L21/324 ,  H01L21/784 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7397

Abstract: According to embodiments, a method for manufacturing a semiconductor device includes forming a mask comprising a pattern of inert structures on a side of a first main surface of a semiconductor substrate. A semiconductor layer is formed over the first main surface, and the semiconductor substrate is thinned from a second main surface opposite to the first main surface. Thereafter, a semiconductor region laterally adjoining the inert structures is anisotropically etched.

公开(公告)号：US09875926B2

公开(公告)日：2018-01-23

申请号：US14953362

申请日：2015-11-29

Applicant: Infineon Technologies AG

Inventor： Iris Moder ,  Ingo Muri ,  Johannes Baumgartl ,  Oliver Hellmund ,  Manfred Engelhardt ,  Hans-Joachim Schulze

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/20 ,  H01L21/02

CPC classification number: H01L21/76267 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/02647 ,  H01L21/2022 ,  H01L21/31144 ,  H01L21/7621 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/76264 ,  H01L21/76272 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/76289 ,  H01L21/76297

Abstract: A method for fabricating a semiconductor device includes forming an opening in a first epitaxial lateral overgrowth region to expose a surface of the semiconductor substrate within the opening. The method further includes forming an insulation region at the exposed surface of the semiconductor substrate within the opening and filling the opening with a second semiconductor material to form a second epitaxial lateral overgrowth region using a lateral epitaxial growth process.

公开(公告)号：US20160203977A1

公开(公告)日：2016-07-14

申请号：US14594838

申请日：2015-01-12

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Ingo Muri ,  Iris Moder

IPC: H01L21/02 ,  H01L21/225 ,  H01L21/74

CPC classification number: H01L21/02258 ,  H01L21/02238 ,  H01L21/2252 ,  H01L21/74 ,  H01L21/78

Abstract: In accordance with a method of manufacturing a semiconductor arrangement, a first trench is formed into a semiconductor body from a first side. An anodic oxide structure is formed at a bottom side of the first trench by immersing the semiconductor body in an electrolyte and applying an anodizing voltage between the semiconductor body and an electrode in contact with the electrolyte.

Abstract translation: 根据制造半导体装置的方法，从第一侧将第一沟槽形成为半导体本体。 通过将半导体本体浸入电解质中并在半导体本体和与电解质接触的电极之间施加阳极氧化电压，在第一沟槽的底侧形成阳极氧化物结构。

公开(公告)号：US09293330B2

公开(公告)日：2016-03-22

申请号：US14011832

申请日：2013-08-28

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Ingo Muri ,  Friedrich Kroener ,  Werner Schustereder

IPC: H01L21/322 ,  H01L29/868 ,  H01L21/265 ,  H01L21/263 ,  H01L21/324 ,  H01L21/3063

CPC classification number: H01L21/26513 ,  H01L21/263 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/3063 ,  H01L21/3242

Abstract: A method for producing a semiconductor is disclosed, the method having: providing a semiconductor body having a first side and a second side; forming an n-doped zone in the semiconductor body by a first implantation into the semiconductor body via the first side to a first depth location of the semiconductor body; and forming a p-doped zone in the semiconductor body by a second implantation into the semiconductor body via the second side to a second depth location of the semiconductor body, a pn-junction forming between said n-doped zone and said p-doped zone in the semiconductor body.

Abstract translation: 公开了一种制造半导体的方法，该方法具有：提供具有第一面和第二面的半导体本体; 通过所述半导体本体中的所述第一侧至所述半导体本体的第一深度位置的第一注入而在所述半导体本体中形成n掺杂区; 以及通过所述半导体本体中的所述第二侧到所述半导体本体的第二深度位置的第二注入在所述半导体本体中形成p掺杂区，在所述n掺杂区和所述p掺杂区之间形成pn结 在半导体体内。

公开(公告)号：US20150064890A1

公开(公告)日：2015-03-05

申请号：US14011832

申请日：2013-08-28

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Ingo Muri ,  Fritz Kroener ,  Werner Schustereder

IPC: H01L21/265

CPC classification number: H01L21/26513 ,  H01L21/263 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/3063 ,  H01L21/3242

Abstract: A method for producing a semiconductor is disclosed, the method having: providing a semiconductor body having a first side and a second side; forming an n-doped zone in the semiconductor body by a first implantation into the semiconductor body via the first side to a first depth location of the semiconductor body; and forming a p-doped zone in the semiconductor body by a second implantation into the semiconductor body via the second side to a second depth location of the semiconductor body, a pn-junction forming between said n-doped zone and said p-doped zone in the semiconductor body.

Abstract translation: 公开了一种制造半导体的方法，该方法具有：提供具有第一面和第二面的半导体本体; 通过所述半导体本体中的所述第一侧至所述半导体本体的第一深度位置的第一注入而在所述半导体本体中形成n掺杂区; 以及通过所述半导体本体中的所述第二侧到所述半导体本体的第二深度位置的第二注入在所述半导体本体中形成p掺杂区，在所述n掺杂区和所述p掺杂区之间形成pn结 在半导体体内。

公开(公告)号：US11810779B2

公开(公告)日：2023-11-07

申请号：US17841781

申请日：2022-06-16

Applicant: Infineon Technologies AG

Inventor： Sophia Friedler ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri

IPC: H01L21/02 ,  H01L21/465 ,  H01L21/8258

CPC classification number: H01L21/0203 ,  H01L21/02019 ,  H01L21/465 ,  H01L21/8258

Abstract: A method includes: in a semiconductor wafer having a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a front surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer, wherein forming the porous region comprises bringing in contact a porosifying agent with the front surface of the first semiconductor layer and applying a voltage between the first semiconductor layer and a first electrode that is in contact with the porosifying agent, wherein applying the voltage comprises applying the voltage between the first electrode and an edge region of the first semiconductor layer.

公开(公告)号：US10535553B2

公开(公告)日：2020-01-14

申请号：US15951995

申请日：2018-04-12

Applicant: Infineon Technologies AG

Inventor： Oliver Hellmund ,  Ingo Muri ,  Johannes Baumgartl ,  Iris Moder ,  Thomas Christian Neidhart ,  Hans-Joachim Schulze

IPC: H01L29/41 ,  H01L21/762 ,  H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3105

Abstract: A semiconductor device includes a trench extending through a semiconductor substrate and an epitaxial layer disposed over a first side of the semiconductor substrate. The epitaxial layer partially fills a portion of the trench. The semiconductor device further includes a back side metal layer disposed over a second side of the semiconductor substrate. The back side metal layer extends into the trench and fills the remaining portion of the trench. The epitaxial layer partially filling the trench contacts the back side metal layer filling the remaining portion within the trench.

公开(公告)号：US10325804B2

公开(公告)日：2019-06-18

申请号：US15858875

申请日：2017-12-29

Applicant: Infineon Technologies AG

Inventor： Oliver Hellmund ,  Johannes Baumgartl ,  Iris Moder ,  Ingo Muri ,  Thomas Christian Neidhart ,  Hans-Joachim Schulze

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/74

Abstract: In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming openings partially filled with a sacrificial material, where the openings extend into a semiconductor substrate from a first side. A void region is formed in a central region of the openings. An epitaxial layer is formed over the first side of the semiconductor substrate and the openings, where the epitaxial layer covers the void region. From a second side of the semiconductor substrate opposite to the first side, the semiconductor substrate is thinned to expose the sacrificial material. The sacrificial material in the openings is removed and the epitaxial layer is exposed. A conductive material is deposited on the exposed surface of the epitaxial layer.

公开(公告)号：US20190096758A1

公开(公告)日：2019-03-28

申请号：US16144169

申请日：2018-09-27

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Bernhard Goller

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/302 ,  H01L21/321 ,  H01L21/78

Abstract: A method for manufacturing a semiconductor device includes: partially dicing a substrate wafer arrangement having a plurality of semiconductor chips, wherein the partial dicing forms trenches around the semiconductor chips on a front-side of the substrate wafer arrangement, the depth being greater than a target thickness of a semiconductor chip; filling the trenches with a polymer material to form a polymer structure; first thinning of the back-side to expose portions of the polymer structure; forming a conductive layer on the back-side of the substrate wafer arrangement so that the exposed portions of the polymer structure are covered; second thinning of the back-side to form insular islands of conductive material, the insular islands separated from each other by the polymer structure, each insular island corresponding to a respective one of the semiconductor chips; and dicing the substrate wafer arrangement along the polymer structure.