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公开(公告)号：US11329608B1
公开(公告)日：2022-05-10
申请号：US17078484
申请日：2020-10-23
Applicant: Infineon Technologies AG
Inventor： Mihail Jefremow , Rex Kho , Ralph Mueller-Eschenbach , Juergen Schaefer , Arndt Voigtlaender , Wei Wang
Abstract: Systems, methods, and circuits are provided for facilitating negative resistance margin testing in an oscillator circuit. An example oscillator circuit includes amplifier circuitry configured to be coupled in parallel with a resonator and variable resistance circuitry configured to, in response to a resistance control signal, adjust a resistance of the oscillator circuit.
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公开(公告)号：US20220085824A1
公开(公告)日：2022-03-17
申请号：US17467767
申请日：2021-09-07
Applicant: Infineon Technologies AG
Inventor： Mihail Jefremow , Ketan Dewan , Rex Kho , Ralph Mueller-Eschenbach , Juergen Schaefer
IPC: H03M1/12 , G06F1/10 , G01R31/317
Abstract: A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.
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公开(公告)号：US20210382776A1
公开(公告)日：2021-12-09
申请号：US16891312
申请日：2020-06-03
Applicant: Infineon Technologies AG
Inventor： Ketan Dewan , Juergen Schaefer
Abstract: A fault check circuit, including a first channel comparator to output a first channel comparator output signal indicating whether a first channel digital signal is outside of a first channel threshold range, wherein the first channel digital signal is A/D converted from a first channel analog signal; a second channel comparator to output a second channel comparator output signal indicating whether a second channel digital signal is outside of a second channel threshold range, wherein the second channel digital signal is A/D converted from a second channel analog signal; and an alarm generator circuit to combine the first and second channel comparator output signals, and output a fault check signal, wherein the first and second channel comparators and the alarm generator circuit are implemented in hardware, and the fault check circuit performs a fault check without software intervention.
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公开(公告)号：US10198332B2
公开(公告)日：2019-02-05
申请号：US15288434
申请日：2016-10-07
Applicant: Infineon Technologies AG
Inventor： Varun Kumar , Sandeep Naduvalamane , Sumit Khandelwal , Puneetha Mukherjee , Juergen Schaefer
Abstract: Methods and systems for checking the integrity of a system on chip (SOC) are described. The SOC can include a controller and one or more registers. Register value(s) from the register(s) can be obtained at a first time to generate a first set of register values. Process(es) of the SOC are executed at a second time after the first time. Register values can again be obtained from the registers at a third time after the second time to generate a second set of register values. The first set of register values can be compared with the second set of register values. Based on the comparison, an operating mode of the SOC can be adjusted. The SOC integrity verification system and method can be used in safety and/or monitoring application(s), such as ASIL applications. For example, the system and method can be used in partial or fully autonomous (self-driving) automotive systems.
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15.发明申请公开(公告)号：US20180364326A1
公开(公告)日：2018-12-20
申请号：US16011657
申请日：2018-06-19
Applicant: Infineon Technologies AG
Inventor： Ketan Dewan , Reinhard Kussian , Juergen Schaefer
IPC: G01S7/282
Abstract: In various embodiments, a circuitry configured to generate a voltage is provided. The circuitry may include a sequence generator configured to provide a sequence of data words consisting of bits. The number of bits is greater than two. The circuitry may further include a delta-sigma modulator configured to receive the sequence of data words provided by the sequence generator and to provide a delta-sigma modulated first single bit data stream at a first data rate, and a decimation filter configured to generate a stream of decimated data words from the first single bit data stream at a second data rate. The second data rate may be smaller than the first data rate, each decimated data word including a plurality of bits. The circuitry may further include a parallel-to-serial converter configured to convert the decimated data words to a second single bit data stream while preserving the second data rate.
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Patent Agency Ranking
公开(公告)号：US20180234103A1
公开(公告)日：2018-08-16
申请号：US15895453
申请日：2018-02-13
Applicant: Infineon Technologies AG
Inventor： Jens Barrenscheen , Peter Bogner , Juergen Schaefer
IPC: H03M1/12
CPC classification number: H03M1/1245 , H02M3/33546 , H02P27/06 , H03M1/0624 , H03M1/122
Abstract: An Analog-to-Digital-Conversion control system includes a first sample and hold circuit configured to provide a first sampled output to be converted by an Analog-to-Digital-Converter, which comprises a first sampling control circuit configured to receive a first trigger information to trigger sampling of a first analog input and to receive a first collision detection information from the Analog-to-Digital-Converter to detect a collision, a first sample and hold stage coupled to the first sampling control circuit and configured to sample the first analog input, only if no collision has been detected by the first sampling control circuit, wherein the first sampling control circuit is further configured to check predefined first sampling criteria and to output a first conversion request to the Analog-to-Digital-Converter, only if the predefined first sampling criteria are fulfilled.
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公开(公告)号：US09528625B2
公开(公告)日：2016-12-27
申请号：US13776760
申请日：2013-02-26
Applicant: Infineon Technologies AG
Inventor： Christian Schweikert , Juergen Schaefer
CPC classification number: F16K31/0648 , F02D41/20 , F02D2041/2051 , F02D2041/2058 , F02D2041/2068 , F02D2041/286 , F16K31/0675 , H01F7/064 , Y10T137/0318
Abstract: A current driving system for a solenoid valve is described herein. In an embodiment, the current driving system comprises a pre-driver to control a control input of a transistor coupled to an electrical input of a solenoid valve. The transistor inducts electric power into the solenoid valve when the transistor is switched on.The current driving system further comprises a signal generator to produce a small signal and to output the small signal to the electrical input of the solenoid valve. The electric power being supplied by the small signal into the solenoid valve is substantially smaller than the electric power being supplied by the transistor when the transistor is switched on. The current driving system further comprises a measurement unit to measure a response to the small signal at the electrical input of the solenoid valve.
Abstract translation: 当前的驱动系统还包括产生小信号的信号发生器，并将小信号输出到电磁阀的电输入端。 由小信号供给到电磁阀中的电力比晶体管接通时由晶体管提供的电力小得多。 当前的驱动系统还包括测量单元，用于测量在电磁阀的电输入处对小信号的响应。
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公开(公告)号：US11831306B2
公开(公告)日：2023-11-28
申请号：US17836181
申请日：2022-06-09
Applicant: Infineon Technologies AG
Inventor： Mihail Jefremow , David Zipperstein , Juergen Schaefer , Holger Dienst , Markus Bichl , Ralph Mueller-Eschenbach , Arndt Voigtlaender
Abstract: According to an example, an electronic device includes a component, a supply line providing a supply voltage, a transistor with a control input, a linear first control loop, and a non-linear second control loop. The transistor outputs an output voltage to the component depending on a signal applied to the control input. The linear first control loop includes an ADC to convert an analog output voltage level into a digital measurement signal, a controller to generate a digital control signal for the transistor depending on the digital measurement signal, and a DAC to convert the digital control signal into a first analog control signal. The non-linear second control loop is configured to generate a second analog control signal depending on the analog output voltage level. The second analog control signal is superimposed with the first analog control signal and the combined control signals are fed to the control input of the transistor.
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公开(公告)号：US11177987B1
公开(公告)日：2021-11-16
申请号：US17081433
申请日：2020-10-27
Applicant: Infineon Technologies AG
Inventor： Mihail Jefremow , Michael Augustin , Ketan Dewan , Ralph Mueller-Eschenbach , Juergen Schaefer
Abstract: Processing a resolver signal by a microcontroller includes generating, by a carrier signal generator, a carrier signal for output to a resolver; receiving modulated carrier signals from a resolver via hardware that is external to the microcontroller; integrating, by an integrator, respective integrator input signals which are based on the modulated carrier signals, to generate respective envelope signals, wherein a start of an integration window of the integrator is set with respect to a start of the carrier signal; and determining an angular position sensed by the resolver based on the envelope signals.
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20.发明授权公开(公告)号：US10816642B2
公开(公告)日：2020-10-27
申请号：US16011657
申请日：2018-06-19
Applicant: Infineon Technologies AG
Inventor： Ketan Dewan , Reinhard Kussian , Juergen Schaefer
IPC: G01S7/282 , G01S7/03 , G01S13/931
Abstract: In various embodiments, a circuitry configured to generate a voltage is provided. The circuitry may include a sequence generator configured to provide a sequence of data words consisting of bits. The number of bits is greater than two. The circuitry may further include a delta-sigma modulator configured to receive the sequence of data words provided by the sequence generator and to provide a delta-sigma modulated first single bit data stream at a first data rate, and a decimation filter configured to generate a stream of decimated data words from the first single bit data stream at a second data rate. The second data rate may be smaller than the first data rate, each decimated data word including a plurality of bits. The circuitry may further include a parallel-to-serial converter configured to convert the decimated data words to a second single bit data stream while preserving the second data rate.
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