公开(公告)号：US11515264B2

公开(公告)日：2022-11-29

申请号：US16421707

申请日：2019-05-24

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez ,  Alexander Breymesser ,  Erich Griebl ,  Michael Knabl ,  Matthias Kuenle ,  Andreas Moser ,  Roland Rupp ,  Hans-Joachim Schulze ,  Sokratis Sgouridis ,  Stephan Voss

IPC: H01L23/00 ,  H01L23/16

Abstract: A method for processing a semiconductor wafer is proposed. The method may include reducing a thickness of the semiconductor wafer. A carrier structure is placed on a first side of the semiconductor wafer, e.g. before or after reducing the thickness of the semiconductor wafer. The method further includes providing a support structure on a second side of the semiconductor wafer opposite to the first side, e.g. after reducing the thickness of the semiconductor wafer. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.

公开(公告)号：US20220359428A1

公开(公告)日：2022-11-10

申请号：US17869114

申请日：2022-07-20

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez ,  Alexander Breymesser ,  Erich Griebl ,  Michael Knabl ,  Matthias Kuenle ,  Andreas Moser ,  Roland Rupp ,  Hans-Joachim Schulze ,  Sokratis Sgouridis ,  Stephan Voss

IPC: H01L23/00 ,  H01L23/16

Abstract: A method for processing a semiconductor wafer is proposed. The method may include: reducing a thickness of the semiconductor wafer; before or after reducing the thickness of the semiconductor wafer, placing a carrier structure at a first side of the semiconductor wafer; and after reducing the thickness of the semiconductor wafer, providing a support structure at a second side of the semiconductor wafer opposite to the first side. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.

公开(公告)号：US11004963B2

公开(公告)日：2021-05-11

申请号：US16202567

申请日：2018-11-28

Applicant: Infineon Technologies AG

Inventor： Oana Julia Spulber ,  Matthias Kuenle ,  Wolfgang Roesner ,  Christian Philipp Sandow ,  Christoph Weiss

IPC: H01L29/739 ,  H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/10 ,  H01L29/32 ,  H01L29/36 ,  H01L29/40 ,  H01L29/08

Abstract: An embodiment relates to a method of manufacturing an insulated gate bipolar transistor in a semiconductor body. A first field stop zone portion of a first conductivity type is formed on a semiconductor substrate. A second field stop zone portion of the first conductivity type is formed on the first field stop zone portion. A drift zone of the first conductivity type is formed on the second field stop zone portion. A doping concentration in the drift zone is smaller than 1013 cm−3 along a vertical extension of more than 30% of a thickness of the semiconductor body upon completion of the insulated gate bipolar transistor.

公开(公告)号：US20180166324A1

公开(公告)日：2018-06-14

申请号：US15833781

申请日：2017-12-06

Applicant: Infineon Technologies AG

Inventor： Carsten Schaeffer ,  Andreas Moser ,  Matthias Kuenle ,  Matteo Dainese ,  Roland Rupp ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/76248 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02647 ,  H01L21/02667 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/823481 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/08 ,  H01L29/0804 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/10 ,  H01L29/1095 ,  H01L29/66 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7812 ,  H01L29/7813

Abstract: A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes. A semiconductor layer is formed over the buried insulation region at a first side of the substrate. Device regions are formed in the semiconductor layer. The substrate is thinned from a second side of the substrate to expose the buried insulation region. The buried insulation region is selectively removed to expose a bottom surface of the substrate. A conductive region is formed under the bottom surface of the substrate.

公开(公告)号：US20220037165A1

公开(公告)日：2022-02-03

申请号：US17386699

申请日：2021-07-28

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Alexander Breymesser ,  Bernhard Goller ,  Matthias Kuenle ,  Helmut Oefner ,  Francisco Javier Santos Rodriguez ,  Stephan Voss

IPC: H01L21/324 ,  H01L21/265 ,  H01L21/78

Abstract: A method of forming a semiconductor device, including forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate, increasing the porosity of the first semiconductor layer, first annealing the first semiconductor layer at a temperature of at least 1050° C., forming a second semiconductor layer on the first semiconductor layer and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer.

公开(公告)号：US20220018023A1

公开(公告)日：2022-01-20

申请号：US17370386

申请日：2021-07-08

Applicant: Infineon Technologies AG

Inventor： Matthias Kuenle ,  Olaf Fiedler ,  Thomas Huber ,  Christian Illemann ,  Mathias Male

IPC: C23C16/455 ,  C23C16/46

Abstract: A processing chamber includes a chamber body, a substrate support configured to hold a substrate in place, and a pre-heat ring having a central opening sized to be disposed around the substrate. A process gas inlet is configured to direct process gas in a lateral direction to flow over the pre-heat ring and the substrate. A process gas flow deflector includes a radially outer mounting portion and a radially inner blade-shaped process gas deflection portion extending in a radial direction. The radially inner blade-shaped process gas deflection portion is shaped as a ring segment. The radially inner blade-shaped process gas deflection portion is disposed above the process gas inlet and dimensioned to overlap with the pre-heat ring, wherein a degree of overlap between the pre-heat ring and process gas flow deflector in the radial direction is at least ½ of the radial dimension of the pre-heat ring.

公开(公告)号：US11149351B2

公开(公告)日：2021-10-19

申请号：US15700232

申请日：2017-09-11

Applicant: Infineon Technologies AG

Inventor： Matthias Kuenle ,  Johannes Baumgartl ,  Manfred Engelhardt ,  Christian Illemann ,  Francisco Javier Santos Rodriguez ,  Olaf Storbeck

IPC: C23C16/54 ,  C23C16/455 ,  C30B25/12 ,  C23C16/458 ,  C23C16/46 ,  C23C16/02 ,  C30B25/10 ,  C30B25/14 ,  H01L21/02 ,  C30B29/06 ,  C30B29/36

Abstract: A CVD reactor, including a deposition chamber housing a first susceptor and a second susceptor, the first susceptor having a cavity for receiving a first substrate, the first substrate having a front surface and a back surface, the second susceptor having a cavity for receiving a second substrate, the second substrate having a front surface and a back surface, and the first susceptor and the second susceptor are disposed so that the front surface of the first substrate is opposite to the front surface of the second substrate thereby forming a portion of a gas flow channel.

公开(公告)号：US10825716B2

公开(公告)日：2020-11-03

申请号：US16192277

申请日：2018-11-15

Applicant: Infineon Technologies AG

Inventor： Andreas Moser ,  Matteo Dainese ,  Matthias Kuenle ,  Hans-Joachim Schulze

IPC: H01L21/02 ,  H01L21/78 ,  H01L21/762 ,  H01L21/324 ,  H01L21/683 ,  H01L23/00 ,  H01L29/73 ,  H01L29/739

Abstract: An embodiment of a method for manufacturing a semiconductor device includes: providing a monocrystalline semiconductor substrate having a first side; forming a plurality of recess structures in the semiconductor substrate at the first side; filling the recess structures with a dielectric material to form dielectric islands in the recess structures; forming a semiconductor layer on the first side of the semiconductor substrate to cover the dielectric islands; and subjecting the semiconductor layer to heat treatment and recrystallizing the semiconductor layer to form a recrystallized semiconductor layer, so that a crystal structure of the recrystallized semiconductor layer adapts to a crystal structure of the semiconductor substrate, and so that the semiconductor substrate and the semiconductor layer together form a compound wafer with the dielectric islands at least partially buried in the semiconductor material of the compound wafer.

公开(公告)号：US10727311B2

公开(公告)日：2020-07-28

申请号：US16050163

申请日：2018-07-31

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Johannes Konrad Baumgartl ,  Matthias Kuenle ,  Erwin Lercher ,  Daniel Schloegl

IPC: H01L29/66 ,  C30B25/00 ,  C30B31/22 ,  C30B31/02 ,  H01L21/225 ,  C30B15/00 ,  C30B15/20 ,  H01L21/02 ,  C30B29/06 ,  H01L29/10

Abstract: A method for forming a power semiconductor device is provided. The method includes: providing a semiconductor wafer grown by a Czochralski process and having a first side; forming an n-type substrate doping layer in the semiconductor wafer at the first side, the substrate doping layer having a doping concentration of at least 1017/cm3; and forming an epitaxy layer on the first side of the semiconductor wafer after forming the n-type substrate doping layer.

公开(公告)号：US10529809B2

公开(公告)日：2020-01-07

申请号：US16235726

申请日：2018-12-28

Applicant: Infineon Technologies AG

Inventor： Matthias Kuenle ,  Daniel Schloegl ,  Hans-Joachim Schulze ,  Christoph Weiss

IPC: H01L29/36 ,  H01L29/78 ,  H01L29/739 ,  H01L29/861 ,  H01L29/10 ,  H01L29/08 ,  H01L21/265 ,  H01L29/66

Abstract: A method of manufacturing a power semiconductor device includes: creating a doped contact region on top of a surface of a carrier; creating, on top of the contact region, a doped transition region having a maximum dopant concentration of at least 0.5*1015 cm−3 for at least 70% of a total extension of the doped transition region in an extension direction and a maximal dopant concentration gradient of at most 3*1022 cm−4, wherein a lower subregion of the doped transition region is in contact with the contact region and has a maximum dopant concentration at least 100 times higher than a maximum dopant concentration of an upper subregion of the doped transition region; and creating a doped drift region on top of the upper subregion of the doped transition region, the doped drift region having a lower dopant concentration than the upper subregion of the doped transition region.