公开(公告)号：US12107130B2

公开(公告)日：2024-10-01

申请号：US17235989

申请日：2021-04-21

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Johannes Konrad Baumgartl ,  Oliver Hellmund ,  Jacob Tillmann Ludwig ,  Iris Moder ,  Thomas Neidhart ,  Gerhard Schmidt ,  Hans-Joachim Schulze

IPC: H01L29/36 ,  H01L21/02 ,  H01L21/223 ,  H01L21/225 ,  H01L21/265 ,  H01L29/167

CPC classification number: H01L29/36 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/2236 ,  H01L21/2253 ,  H01L21/26513 ,  H01L29/167

Abstract: A semiconductor device includes a semiconductor substrate having a first dopant and a second dopant. A covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent atomic radius of the second dopant. The semiconductor device further includes a semiconductor layer on the semiconductor substrate and semiconductor device elements in the semiconductor layer. A vertical concentration profile of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate and the semiconductor layer to a surface of the semiconductor substrate opposite to the interface.

公开(公告)号：US20200335579A1

公开(公告)日：2020-10-22

申请号：US16851479

申请日：2020-04-17

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Elmar Falck

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10

Abstract: A semiconductor device includes: a semiconductor body with an edge region arranged between an inner region and an edge surface; a first semiconductor region of a first doping type in the inner region; and a second semiconductor region of a second doping type in the inner and edge regions. An edge termination structure includes: a third semiconductor region in the edge region adjoining the first semiconductor region; a surface section of the second semiconductor region adjoining a first main surface of the semiconductor body; and an amorphous passivation layer having a specific resistance higher than 109 Ωcm adjoining the third semiconductor region and the surface section. An electrically active doping dose of the third region at a lateral position spaced apart from the first region by 50% of a width of the edge termination structure is at least QBR/q, wherein QBR is breakdown charge and q is elementary charge.

公开(公告)号：US10008590B2

公开(公告)日：2018-06-26

申请号：US15367633

申请日：2016-12-02

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt

IPC: H01L29/739 ,  H01L27/06 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/36

CPC classification number: H01L29/7396 ,  H01L27/0635 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/7395 ,  H01L29/7432 ,  H01L29/7811 ,  H01L29/8613

Abstract: A semiconductor device is provide that includes: a semiconductor body having a first surface, an inner region, and an edge region; a pn junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the pn-junction extending in a lateral direction of the semiconductor body in the inner region; a recess extending from the first surface in the edge region into the semiconductor body, the recess comprising at least one sidewall; a dielectric filling the recess. In the dielectric, a dielectric number, in the lateral direction, decreases as a distance from the first sidewall increases.

公开(公告)号：US09349799B2

公开(公告)日：2016-05-24

申请号：US14825231

申请日：2015-08-13

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Josef Georg Bauer ,  Mario Barusic ,  Oliver Humbel ,  Hans Millonig ,  Werner Schustereder

IPC: H01L21/332 ,  H01L29/10 ,  H01L29/66 ,  H01L29/739 ,  H01L29/08 ,  H01L21/266 ,  H01L21/225 ,  H01L21/263

CPC classification number: H01L29/1095 ,  H01L21/225 ,  H01L21/2636 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/3221 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/167 ,  H01L29/207 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66272 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/732 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/8611

Abstract: Disclosed are a method and a semiconductor device. The method includes implanting recombination center atoms via a first surface into a semiconductor body, and causing the implanted recombination center atoms to diffuse in the semiconductor body in a first diffusion process.

Abstract translation: 公开了一种方法和半导体器件。 该方法包括通过第一表面将复合中心原子注入到半导体本体中，并且使得注入的复合中心原子在第一扩散过程中在半导体本体中扩散。

公开(公告)号：US20160086854A1

公开(公告)日：2016-03-24

申请号：US14960505

申请日：2015-12-07

Applicant: Infineon Technologies AG

Inventor： Alexander Breymesser ,  Andre Brockmeier ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze ,  Carsten von Koblinski ,  Gerhard Schmidt

IPC: H01L21/78 ,  H01L23/00 ,  H01L29/861 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L21/78 ,  H01L21/2007 ,  H01L21/56 ,  H01L21/76224 ,  H01L23/3178 ,  H01L23/564 ,  H01L29/7393 ,  H01L29/78 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a glass piece and an active semiconductor element formed in a single-crystalline semiconductor portion. The single-crystalline semiconductor portion has a working surface, a rear side surface opposite to the working surface and an edge surface connecting the working and rear side surfaces. The glass piece has a portion extending along and in direct contact with the edge surface of the single-crystalline semiconductor portion.

Abstract translation: 半导体器件包括形成在单晶半导体部分中的玻璃片和有源半导体元件。 单晶半导体部分具有工作表面，与工作表面相对的后侧表面和连接工作表面和后侧表面的边缘表面。 玻璃片具有沿着单晶半导体部分的边缘表面延伸并与之直接接触的部分。

公开(公告)号：US20150294868A1

公开(公告)日：2015-10-15

申请号：US14253519

申请日：2014-04-15

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Josef Riss ,  Thomas Neidhart

IPC: H01L21/225 ,  H01L29/167 ,  H01L29/36 ,  H01L21/322

CPC classification number: H01L29/36 ,  H01L21/26506 ,  H01L21/3225

Abstract: Chalcogen atoms are implanted into a single crystalline semiconductor substrate. At a density of interstitial oxygen of at least 5E16 cm−3 thermal donors containing oxygen are generated at crystal defects in the semiconductor substrate. Then the semiconductor substrate is heated up to a temperature above a deactivation temperature at which the thermal donors become inactive, wherein a portion of electrically active chalcogen atoms is increased.

Abstract translation: 将硫族原子注入单晶半导体衬底中。 在至少5E16cm-3的间隙氧的密度下，在半导体衬底中的晶体缺陷处产生含有氧的热供体。 然后将半导体衬底加热到​​高于失活温度的温度，在此温度下，供体不活跃，其中一部分电活性硫属原子增加。

公开(公告)号：US20150279968A1

公开(公告)日：2015-10-01

申请号：US14736420

申请日：2015-06-11

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/765 ,  H01L21/266

CPC classification number: H01L29/66681 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/765 ,  H01L29/0611 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/861

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate having first and second sides, laterally spaced semiconductor devices integrated into the semiconductor substrate, and a drift region of a first conductivity type. Trenches are formed in the semiconductor substrate at the first side of the semiconductor substrate between laterally adjacent semiconductor devices, each of the trenches having two sidewalls and a bottom. First doping zones of a second conductivity type are formed in the semiconductor substrate at least along the sidewalls of the trenches. The first doping zones form pn-junctions with the drift region. Second doping zones of the first conductivity type are formed in the semiconductor substrate at least along a part of the bottom of the trenches. The second doping zones adjoin the drift region. The semiconductor substrate is cut along the second doping zones in the trenches to separate the semiconductor devices.

Abstract translation: 一种制造半导体器件的方法包括提供具有第一和第二侧面的半导体衬底，集成到半导体衬底中的横向间隔开的半导体器件以及第一导电类型的漂移区域。 在半导体衬底的半导体衬底的横向相邻半导体器件之间的半导体衬底中形成沟槽，每个沟槽具有两个侧壁和底部。 至少沿着沟槽的侧壁在半导体衬底中形成第二导电类型的第一掺杂区。 第一掺杂区与漂移区形成pn结。 至少沿着沟槽的底部的一部分，在半导体衬底中形成第一导电类型的第二掺杂区。 第二掺杂区毗邻漂移区。 沿着沟槽中的第二掺杂区切割半导体衬底以分离半导体器件。

公开(公告)号：US20150056788A1

公开(公告)日：2015-02-26

申请号：US14502882

申请日：2014-09-30

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Josef-Georg Bauer ,  Carsten Schaeffer ,  Oliver Humbel ,  Angelika Koprowski ,  Sirinpa Monayakul

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/283 ,  H01L29/47

CPC classification number: H01L29/66143 ,  H01L21/02115 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/283 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/408 ,  H01L29/47 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.

Abstract translation: 半导体器件包括具有第一表面的半导体本体，布置在第一表面上的接触电极以及与接触电极相邻的第一表面上的钝化层。 钝化层包括在第一表面上具有非晶半绝缘层的层叠层，非晶半绝缘层上的第一氮化物层和第一氮化物层上的第二氮化物层。

公开(公告)号：US20150001719A1

公开(公告)日：2015-01-01

申请号：US13927923

申请日：2013-06-26

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Matthias Müller ,  Francisco Javier Santos Rodriguez ,  Daniel Schlögl

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76841 ,  H01L29/0615 ,  H01L29/0619

Abstract: A power semiconductor device includes a semiconductor body, having an active zone and a high voltage peripheral zone laterally adjacent to each other, the high voltage peripheral zone laterally surrounding the active zone. The device further includes a metallization layer on a front surface of the semiconductor body and connected to the active zone, a first barrier layer, comprising a high-melting metal or a high-melting alloy, between the active zone and the metallization layer, and a second barrier layer covering at least a part of the peripheral zone, the second barrier layer comprising an amorphous semi-isolating material. The first barrier layer and the second barrier layer partially overlap and form an overlap zone. The overlap zone extends over an entire circumference of the active zone. A method for producing such a power semiconductor device is also provided.

Abstract translation: 功率半导体器件包括具有横向相邻的有源区和高电压周边区的半导体本体，所述高电压周边区横向围绕有源区。 该器件还包括在半导体主体的前表面上并连接到有源区的金属化层，在活性区和金属化层之间包括高熔点金属或高熔点合金的第一阻挡层，以及 覆盖所述周边区域的至少一部分的第二阻挡层，所述第二阻挡层包括非晶半隔离材料。 第一阻挡层和第二阻挡层部分地重叠并形成重叠区域。 重叠区域在活动区域​​的整个圆周上延伸。 还提供了一种用于制造这种功率半导体器件的方法。

公开(公告)号：US20130119522A1

公开(公告)日：2013-05-16

申请号：US13709786

申请日：2012-12-10

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Hans-Joachim Schulze ,  Bernd Kolbesen

IPC: H01L29/06

CPC classification number: H01L29/0607 ,  H01L21/223 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1016 ,  H01L29/167 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66363 ,  H01L29/66712 ,  H01L29/66909 ,  H01L29/7397 ,  H01L29/7802

Abstract: A semiconductor substrate includes a first side and a second side opposite the first side. A semiconductor material extends between the first and second sides and is devoid of active device regions. The semiconductor material has a first region and a second region. The first region extends from the first side to a depth into the semiconductor material and includes chalcogen dopant atoms which provide a base doping concentration for the first region. The second region extends from the first region to the second side and is devoid of base doping. Further, a power semiconductor component is provided.

Abstract translation: 半导体衬底包括与第一侧相对的第一侧和第二侧。 半导体材料在第一和第二侧之间延伸并且没有有源器件区域。 半导体材料具有第一区域和第二区域。 第一区域从第一侧向深度延伸到半导体材料中，并且包括提供第一区域的基极掺杂浓度的硫族化合物掺杂剂原子。 第二区域从第一区域延伸到第二侧并且没有基底掺杂。 此外，提供功率半导体部件。