公开(公告)号：US11437311B2

公开(公告)日：2022-09-06

申请号：US16951556

申请日：2020-11-18

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L21/00 ,  H01L23/498 ,  H01L23/367 ,  H01L23/40 ,  H01L23/31 ,  H01L23/24 ,  H01L21/56 ,  H01L25/07 ,  H01L23/00

Abstract: A method for producing a power semiconductor module arrangement includes arranging two or more individual semiconductor devices on a base layer, each semiconductor device including a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame, arranging a frame on the base layer such that the frame surrounds the two or more individual semiconductor devices, and filling a first material into a capacity formed by the base layer and the frame, and hardening the first material to form a casting compound that at least partly fills the capacity, thereby at least partly encloses the two or more individual semiconductor devices.

公开(公告)号：US09620459B2

公开(公告)日：2017-04-11

申请号：US14476241

申请日：2014-09-03

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/07 ,  H01L25/00 ,  H01L23/051 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/24 ,  H01L24/33 ,  H01L24/72 ,  H01L24/82 ,  H01L24/90 ,  H01L24/96 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/29011 ,  H01L2224/33181 ,  H01L2224/82039 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/35 ,  H01L2924/00

Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.

公开(公告)号：US09589859B2

公开(公告)日：2017-03-07

申请号：US14462693

申请日：2014-08-19

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Edward Fuergut ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/34 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/66 ,  H01L23/522 ,  H01L27/02 ,  H01L23/00 ,  H01L23/051

CPC classification number: H01L21/78 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L22/10 ,  H01L22/14 ,  H01L23/051 ,  H01L23/31 ,  H01L23/522 ,  H01L24/96 ,  H01L25/072 ,  H01L25/115 ,  H01L27/02 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor arrangement includes a plurality of chip assemblies, each of which includes a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally circumferentially in a ring-shaped fashion such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

Abstract translation: 半导体装置包括多个芯片组件，每个芯片组件包括半导体芯片，半导体芯片具有顶侧和下侧的半导体主体，布置在顶侧的顶部主电极，布置在下侧的底部主电极，电气 导电顶部补偿层布置在顶部主电极的背离半导体主体的一侧并且内导电地连接到顶部主电极，导电底部补偿层布置在底部主电极的背离 半导体本体并且内导电地连接到底部主电极，以及环形化方式围绕半导体芯片横向周向的电介质嵌入化合物，使得补偿层的背离半导体本体的一侧至少不是完全的 被包埋化合物覆盖。

公开(公告)号：US09543389B2

公开(公告)日：2017-01-10

申请号：US14102955

申请日：2013-12-11

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Peter Kanschat

IPC: H01L29/96 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/423 ,  H01L29/04 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/1095 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/42368 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/8613

Abstract: A semiconductor device includes a drift zone in a semiconductor body. A charge-carrier transfer region forms a pn junction with the drift zone in the semiconductor body. A control structure electrically connects a recombination region to the drift zone during a desaturation cycle and disconnects the recombination region from the drift zone outside the desaturation cycle. During the desaturation cycle the recombination region reduces a charge carrier plasma in the drift zone and reduces reverse recovery losses without adversely affecting blocking characteristics.

Abstract translation: 半导体器件包括半导体本体中的漂移区。 电荷载流子传输区域与半导体本体中的漂移区形成pn结。 控制结构在去饱和循环期间将复合区域电连接到漂移区，并且将去除饱和循环以外的漂移区域的复合区域断开。 在去饱和循环期间，重组区域减少漂移区中的载流子等离子体并且减少反向回复损耗而不会不利地影响阻塞特性。

公开(公告)号：US20150054166A1

公开(公告)日：2015-02-26

申请号：US14462693

申请日：2014-08-19

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Edward Fuergut ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L21/78 ,  H01L27/02 ,  H01L23/522

CPC classification number: H01L21/78 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L22/10 ,  H01L22/14 ,  H01L23/051 ,  H01L23/31 ,  H01L23/522 ,  H01L24/96 ,  H01L25/072 ,  H01L25/115 ,  H01L27/02 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor arrangement includes a plurality of chip assemblies, each of which includes a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally circumferentially in a ring-shaped fashion such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

Abstract translation: 半导体装置包括多个芯片组件，每个芯片组件包括半导体芯片，半导体芯片具有顶侧和下侧的半导体主体，布置在顶侧的顶部主电极，布置在下侧的底部主电极，电气 导电顶部补偿层布置在顶部主电极的背离半导体主体的一侧并且内导电地连接到顶部主电极，导电底部补偿层布置在底部主电极的背离 半导体本体并且内导电地连接到底部主电极，以及环形化方式围绕半导体芯片横向周向的电介质嵌入化合物，使得补偿层的背离半导体本体的一侧至少不是完全的 被包埋化合物覆盖。

公开(公告)号：US09984928B2

公开(公告)日：2018-05-29

申请号：US15378669

申请日：2016-12-14

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Gottfried Beer ,  Edward Fuergut ,  Juergen Hoegerl ,  Peter Kanschat

IPC: H01L21/44 ,  H01L21/78 ,  H01L21/66 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L21/78 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L22/10 ,  H01L22/14 ,  H01L23/051 ,  H01L23/31 ,  H01L23/522 ,  H01L24/96 ,  H01L25/072 ,  H01L25/115 ,  H01L27/02 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

公开(公告)号：US09818730B2

公开(公告)日：2017-11-14

申请号：US14477386

申请日：2014-09-04

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/48 ,  H01L25/07 ,  H01L23/492 ,  H01L23/495 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/051 ,  H01L23/31

CPC classification number: H01L25/072 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/562 ,  H01L24/24 ,  H01L24/33 ,  H01L24/72 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/29011 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.

公开(公告)号：US20170098580A1

公开(公告)日：2017-04-06

申请号：US15378669

申请日：2016-12-14

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Gottfried Beer ,  Edward Fuergut ,  Juergen Hoegerl ,  Peter Kanschat

IPC: H01L21/78 ,  H01L21/56 ,  H01L21/48 ,  H01L21/66

CPC classification number: H01L21/78 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L22/10 ,  H01L22/14 ,  H01L23/051 ,  H01L23/31 ,  H01L23/522 ,  H01L24/96 ,  H01L25/072 ,  H01L25/115 ,  H01L27/02 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

公开(公告)号：US08994413B2

公开(公告)日：2015-03-31

申请号：US13871288

申请日：2013-04-26

Applicant: Infineon Technologies AG

Inventor： Peter Kanschat ,  Andre Arens ,  Hartmut Jasberg ,  Ulrich Schwarzer

IPC: H03K3/00 ,  H03K17/00 ,  H03K17/16

CPC classification number: H03K17/00 ,  H03K17/163 ,  H03K17/168

Abstract: A method for driving a controllable power semiconductor switch, having a first input terminal and first and second output terminals coupled to a voltage supply and a load, the first and second output terminals providing an output of the power semiconductor switch, includes adjusting a gradient of switch-off edges of an output current and an output voltage of the power semiconductor switch by a voltage source arrangement coupled to the input terminal. A gradient of switch-on edges of an output current and an output voltage is adjusted by a controllable current source arrangement that is coupled to the input terminal and generates a gate drive current. The profile of the gate drive current from one switching operation to a subsequent switching operation, beginning at a rise in the output current and ending at a decrease in the output voltage, is varied at most within a predefined tolerance band.

Abstract translation: 一种用于驱动可控功率半导体开关的方法，具有第一输入端和耦合到电压源和负载的第一和第二输出端，提供功率半导体开关的输出的第一和第二输出端包括： 通过耦合到输入端的电压源装置，输出电流的关断边缘和功率半导体开关的输出电压。 输出电流和输出电压的接通边沿的梯度由耦合到输入端子的可控电流源装置调节并产生栅极驱动电流。 从输出电流的上升开始并以输出电压的降低结束的栅极驱动电流从一个开关操作到随后的开关操作的曲线最多在预定义的公差带内变化。

公开(公告)号：US20150061144A1

公开(公告)日：2015-03-05

申请号：US14476241

申请日：2014-09-03

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/07 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/24 ,  H01L24/33 ,  H01L24/72 ,  H01L24/82 ,  H01L24/90 ,  H01L24/96 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/29011 ,  H01L2224/33181 ,  H01L2224/82039 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/35 ,  H01L2924/00

Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.

Abstract translation: 半导体装置包括上和下接触板和基本芯片组件。 每个芯片组件具有半导体芯片，半导体芯片具有上部和下部间隔开的侧面的半导体本体。 单独的上主电极和单独的控制电极设置在上侧。 芯片组件分别具有布置在相应的基本芯片组件的半导体芯片的下侧上的单独的下部主电极或共同的下部主电极，其中每个芯片组件布置在半导体的下侧 该芯片组件的主体。 各个上主电极和单个或公共下主电极之间的电流可由其控制电极控制。 芯片组件通过电介质嵌入化合物的材料结合连接彼此连接，形成固体组件。