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    Mechanism To Avoid Hot-L1/Cold-L2 Events In An Inclusive L2 Cache Using L1 Presence Bits For Victim Selection Bias
    11.
    发明申请
    Mechanism To Avoid Hot-L1/Cold-L2 Events In An Inclusive L2 Cache Using L1 Presence Bits For Victim Selection Bias 有权
    机制避免热L1 /冷L2事件在一个包含L2缓存使用L1存在位受害者选择偏差

    公开(公告)号：US20160283380A1

    公开(公告)日：2016-09-29

    申请号：US14671411

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Krishna N. Vinod ,  Avinash Sodani ,  Zainulabedin Aurangabadwala

    IPC: G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/0833 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/123 ,  G06F2212/1008

    Abstract: A processor includes a processing core, an L1 cache, operatively coupled to the processing core, the L1 cache comprising an L1 cache entry to store a data item, an L2 cache, inclusive with respect to the L1 cache, the L2 cache comprising an L2 cache entry corresponding to the L1 cache entry, an activity flag associated with the L2 cache entry, the activity flag indicating an activity status of the L1 cache entry, and a cache controller to, in response to detecting an access operation with respect to the L1 cache entry, set the flag to an active status.

    Abstract translation: 处理器包括可操作地耦合到所述处理核心的处理核心，L1高速缓存器，所述L1高速缓存器包括相对于所述L1高速缓存存储数据项的L1高速缓存条目，L2高速缓存，所述L2高速缓存包括L2 对应于L1高速缓存条目的缓存条目，与L2高速缓存条目相关联的活动标志，指示L1高速缓存条目的活动状态的活动标志，以及高速缓存控制器，响应于检测到关于L1的访问操作 缓存条目，将标志设置为活动状态。

    Method and apparatus for user-level thread synchronization with a monitor and MWAIT architecture
    14.
    发明授权
    Method and apparatus for user-level thread synchronization with a monitor and MWAIT architecture 有权

    公开(公告)号：US09898351B2

    公开(公告)日：2018-02-20

    申请号：US14998217

    申请日：2015-12-24

    Applicant: Intel Corporation

    Inventor： Benjamin C. Chaffin ,  Robert J. Kyanko ,  Avinash Sodani

    IPC: G06F9/52 ,  G06F12/0806

    CPC classification number: G06F9/52 ,  G06F12/0806 ,  G06F2201/885 ,  G06F2209/521

    Abstract: Instructions and logic provide user-level thread synchronization with MONITOR and MWAIT instructions. One or more model specific registers (MSRs) in a processor may be configured in a first execution state to specify support of a user-level thread synchronization architecture. Embodiments include multiple hardware threads or processing cores, corresponding monitored address state storage to store a last monitored address for each of a plurality of execution threads that issues a MONITOR request, cache memory to record MONITOR requests and associated states for addresses of memory storage locations, and responsive to receipt of an MWAIT request for the address, to record an associated wait-to-trigger state of monitored addresses for execution cores associated with an MWAIT request; wherein the execution core is to transition a requesting thread to an optimized sleep state responsive to the receipt of said MWAIT request when said one or more MSRs are configured in the first execution state.

    THERMAL THROTTLING OF ELECTRONIC DEVICES
    16.
    发明申请
    THERMAL THROTTLING OF ELECTRONIC DEVICES 审中-公开
    电子设备的热转折

    公开(公告)号：US20160378149A1

    公开(公告)日：2016-12-29

    申请号：US14752512

    申请日：2015-06-26

    Applicant: INTEL CORPORATION

    Inventor： Timothy Y. Kam ,  Sandeep Ahuja ,  Rajat Agarwal ,  Avinash Sodani ,  Jinho Suh ,  Meenakshisundaram Chinthamani

    IPC: G06F1/20 ,  G06F1/32

    CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G06F2212/1028 ,  G11C7/04 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/16

    Abstract: Disclosed herein is a computing device configured to implement thermal throttling of a component of the computing device. The computing device includes an electronic component and a temperature sensor thermally coupled to the electronic component. The computing device also includes a thermal management controller to receive a temperature measurement from the temperature sensor and generate a throttling factor for the electronic component. If the temperature measurement is greater than a specified threshold, the throttling factor is to reduce performance of the electronic component to be at least the performance guarantee for the electronic component.

    Abstract translation: 这里公开了一种被配置为实现计算设备的部件的热调节的计算设备。 计算设备包括热耦合到电子部件的电子部件和温度传感器。 计算设备还包括热管理控制器，用于从温度传感器接收温度测量并产生电子部件的节流因子。 如果温度测量值大于指定的阈值，则节流因素是将电子元件的性能降至至少为电子元件的性能保证。

    Minimizing snoop traffic locally and across cores on a chip multi-core fabric
    18.
    发明授权
    Minimizing snoop traffic locally and across cores on a chip multi-core fabric 有权

    公开(公告)号：US10102129B2

    公开(公告)日：2018-10-16

    申请号：US14976678

    申请日：2015-12-21

    Applicant: Intel Corporation

    Inventor： Krishna N. Vinod ,  Avinash Sodani ,  Zainulabedin J. Aurangabadwala

    IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0811

    Abstract: A processor includes a processing core, a L1 cache comprising a first processing core and a first L1 cache comprising a first L1 cache data entry of a plurality of L1 cache data entries to store data. The processor also includes an L2 cache comprising a first L2 cache data entry of a plurality of L2 cache data entries. The first L2 cache data entry corresponds to the first L1 cache data entry and each of the plurality of L2 cache data entries are associated with a corresponding presence bit (pbit) of a plurality of pbits. Each of the plurality of pbits indicates a status of a corresponding one of the plurality of L2 cache data entries. The processor also includes a cache controller, which in response to a first request among a plurality of requests to access the data at the first L1 cache data entry, determines that a copy of the data is stored in the first L2 cache data entry; and retrieves the copy of the data from the L2 cache data entry in view of the status of the pbit.

    Method and apparatus for user-level thread synchronization with a monitor and MWAIT architecture
    19.
    发明申请
    Method and apparatus for user-level thread synchronization with a monitor and MWAIT architecture 有权

    公开(公告)号：US20170185458A1

    公开(公告)日：2017-06-29

    申请号：US14998217

    申请日：2015-12-24

    Applicant: Intel Corporation

    Inventor： Benjamin C. Chaffin ,  Robert J. Kyanko ,  Avinash Sodani

    IPC: G06F9/52

    CPC classification number: G06F9/52 ,  G06F12/0806 ,  G06F2201/885 ,  G06F2209/521

    Abstract: Instructions and logic provide user-level thread synchronization with MONITOR and MWAIT instructions. One or more model specific registers (MSRs) in a processor may be configured in a first execution state to specify support of a user-level thread synchronization architecture. Embodiments include multiple hardware threads or processing cores, corresponding monitored address state storage to store a last monitored address for each of a plurality of execution threads that issues a MONITOR request, cache memory to record MONITOR requests and associated states for addresses of memory storage locations, and responsive to receipt of an MWAIT request for the address, to record an associated wait-to-trigger state of monitored addresses for execution cores associated with an MWAIT request; wherein the execution core is to transition a requesting thread to an optimized sleep state responsive to the receipt of said MWAIT request when said one or more MSRs are configured in the first execution state.

    MINIMIZING SNOOP TRAFFIC LOCALLY AND ACROSS CORES ON A CHIP MULTI-CORE FABRIC
    20.
    发明申请
    MINIMIZING SNOOP TRAFFIC LOCALLY AND ACROSS CORES ON A CHIP MULTI-CORE FABRIC 审中-公开

    公开(公告)号：US20170177483A1

    公开(公告)日：2017-06-22

    申请号：US14976678

    申请日：2015-12-21

    Applicant: Intel Corporation

    Inventor： Krishna N. Vinod ,  Avinash Sodani ,  Zainulabedin J. Aurangabadwala

    IPC: G06F12/08

    CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F2212/621

    Abstract: A processor includes a processing core, a L1 cache comprising a first processing core and a first L1 cache comprising a first L1 cache data entry of a plurality of L1 cache data entries to store data. The processor also includes an L2 cache comprising a first L2 cache data entry of a plurality of L2 cache data entries. The first L2 cache data entry corresponds to the first L1 cache data entry and each of the plurality of L2 cache data entries are associated with a corresponding presence bit (pbit) of a plurality of pbits. Each of the plurality of pbits indicates a status of a corresponding one of the plurality of L2 cache data entries. The processor also includes a cache controller, which in response to a first request among a plurality of requests to access the data at the first L1 cache data entry, determines that a copy of the data is stored in the first L2 cache data entry; and retrieves the copy of the data from the L2 cache data entry in view of the status of the pbit.

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