公开(公告)号：US20240178084A1

公开(公告)日：2024-05-30

申请号：US18060106

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Soham Agarwal ,  Benjamin T. Duong

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16235 ,  H01L2224/73204

Abstract: Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic assembly may include a core made of glass and having a surface, the core further including a first region having a first concentration of ions and a second region having a second concentration of ions at the surface of the core; and a third region having a third concentration of ions, wherein the second region is between the third region and the surface of the core, and wherein the third concentration of ions is less than the first and second concentrations of ions; a dielectric with a conductive pathway at the surface of the core; and a die electrically coupled to the conductive pathway in the dielectric at the surface of the core by an interconnect.

公开(公告)号：US11948898B2

公开(公告)日：2024-04-02

申请号：US16413943

申请日：2019-05-16

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas V. Pietambaram ,  Hongxia Feng ,  Xiaoying Guo ,  Benjamin T. Duong

IPC: H01L23/66 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/66 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76879 ,  H01L23/5283 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2223/6605

Abstract: Conductive structures in a microelectronic package and having a surface roughness of 50 nm or less are described. This surface roughness is from 2 to 4 times less than can be found in packages with conductive structures (e.g., traces) formed using alternative techniques. This reduced surface roughness has a number of benefits, which in some cases includes a reduction of insertion loss and improves a signal to noise ratio for high frequency computing applications. The reduced surface roughness can be accomplished by protecting the conductive structure r during etch processes and applying an adhesion promoting layer to the conductive structure.

公开(公告)号：US20230420373A1

公开(公告)日：2023-12-28

申请号：US17848069

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Benjamin T. Duong ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/5381 ,  H01L23/3135 ,  H01L23/3121 ,  H01L25/105 ,  H01L24/20 ,  H01L23/5383 ,  H01L24/19 ,  H01L25/50 ,  H01L21/486 ,  H01L21/4857 ,  H01L25/0655 ,  H01L23/49894 ,  H01L2225/1035 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/214 ,  H01L24/32 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/19

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate having a cavity; a first die at least partially nested in the cavity in the first layer of the substrate, the first die having a surface with conductive contacts; a liner layer on the first layer, in a portion of the cavity, and on and around the first die, wherein a material of the liner layer includes: silicon or aluminum, and one or more of nitrogen, oxygen, and carbon; a second layer on the liner layer, wherein the second layer extends into the cavity and is on and around the first die; and a second die on the second layer, wherein the second die is electrically coupled to the conductive contacts on the first die by conductive vias through the second layer and the liner layer.

公开(公告)号：US20220392855A1

公开(公告)日：2022-12-08

申请号：US17342307

申请日：2021-06-08

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Benjamin T. Duong ,  Srinivas V. Pietambaram ,  Thomas Sounart ,  Aleksandar Aleksov ,  Adel A. Elsherbini

IPC: H01L23/58 ,  H01L23/538 ,  H01L49/02 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die in a first dielectric layer; and a capacitor including a first conductive pillar and a second conductive pillar in the first dielectric layer, each pillar having a first end and an opposing second end, where the first and second conductive pillars form a first plate of the capacitor; a second dielectric layer on the die and on the second end of the first and second conductive pillars extending at least partially along a first thickness of the first and second conductive pillars and tapering from the second end towards the first end; and a metal layer on the second dielectric layer, wherein the metal layer extends at least partially along a second thickness of the first and second conductive pillars, where the metal layer forms a second plate of the capacitor.