公开(公告)号：US20220375882A1

公开(公告)日：2022-11-24

申请号：US17323194

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Benjamin T. Duong ,  Srinivas V. Pietambaram ,  Tarek A. Ibrahim

IPC: H01L23/64 ,  H01L23/538 ,  H01L25/065 ,  H01L49/02 ,  H01L21/768 ,  H01F3/10

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, including a first conductive pillar, having a first end at the first surface of the magnetic core inductor and an opposing second end at the second surface, at least partially surrounded by a magnetic material that extends at least partially along a thickness of the first conductive pillar from the second end and tapers towards the first end; and a second conductive pillar coupled to the first conductive pillar; and a second die in a second dielectric layer on the first dielectric layer coupled to the second surface of the magnetic core inductor.

公开(公告)号：US20240178146A1

公开(公告)日：2024-05-30

申请号：US18060080

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Benjamin T. Duong ,  Whitney Bryks ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Ravindranath Vithal Mahajan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L23/15 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/13023 ,  H01L2924/15165 ,  H01L2924/15311

Abstract: Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic assembly may include a glass core having a surface, a first region having a first concentration of ions extending from the surface of the core to a first depth; a second region having a second concentration of ions greater than the first concentration of ions, the second region between the first region and the surface of the core; a dielectric with a conductive pathway at the surface of the glass core; and a die electrically coupled to the conductive pathway in the dielectric at the surface of the core by an interconnect.

公开(公告)号：US20230095846A1

公开(公告)日：2023-03-30

申请号：US17485039

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Benjamin T. Duong ,  Srinivas V. Pietambaram ,  Aleksandar Aleksov ,  Helme Castro De La Torre ,  Kristof Darmawikarta ,  Darko Grujicic ,  Sashi S. Kandanur ,  Suddhasattwa Nad ,  Rengarajan Shanmugam ,  Thomas I. Sounart ,  Marcel A. Wall

IPC: H01L23/498 ,  H01G4/33 ,  H01L21/48

Abstract: Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.

公开(公告)号：US20240222295A1

公开(公告)日：2024-07-04

申请号：US18148598

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Mahdi Mohammadighaleni ,  Joshua Stacey ,  Benjamin T. Duong ,  Thomas S. Heaton ,  Dilan Seneviratne ,  Rahul N. Manepalli

IPC: H01L23/64 ,  H01G4/20 ,  H01G4/33 ,  H01L23/00 ,  H01L23/498 ,  H05K1/16

CPC classification number: H01L23/642 ,  H01G4/206 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H05K1/162 ,  H01L2224/16235 ,  H01L2924/19041 ,  H05K2201/0175

Abstract: Embodiments described herein enable a microelectronic assembly that includes: a package substrate having a core including a solid continuous glass material with one or more capacitors in the solid continuous glass material and integrated circuit (IC) dies coupled to the package substrate. The structure of each capacitor includes a dielectric structure between two conductive structures. The dielectric structure comprises a layer of organic dielectric material between two layers of crystalline inorganic material. The crystalline inorganic material is in direct contact with one of the two conductive structures.

公开(公告)号：US20240219632A1

公开(公告)日：2024-07-04

申请号：US18091535

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Umesh Prasad ,  Suddhasattwa Nad ,  Benjamin T. Duong ,  Yi Yang

IPC: G02B6/122 ,  G02B1/02 ,  G02B3/00

CPC classification number: G02B6/122 ,  G02B1/02 ,  G02B3/0087 ,  G02B2006/12061

Abstract: Technologies for integrated graded index (GRIN) lenses for photonic circuits is disclosed. In one illustrative embodiment, a glass substrate has a cavity in which a GRIN lens is disposed. In other embodiments, the GRIN lens may be on a surface of the glass substrate. The GRIN lens focuses and collimates light to a free-space beam from a waveguide defined in the glass substrate. Another component such as a photonic integrated circuit (PIC) die may also have a GRIN lens and focus the free-space beam into a waveguide in the PIC die. The use of GRIN lenses allows for passive coupling to waveguides without further active alignment that minimizes signal transmission losses.

公开(公告)号：US20230395467A1

公开(公告)日：2023-12-07

申请号：US17833648

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Tarek A. Ibrahim ,  Jeremy D. Ecton ,  Brandon Christian Marin ,  Gang Duan ,  Suddhasattwa Nad ,  Yi Yang ,  Benjamin T. Duong ,  Junxin Wang ,  Sameer R. Paital

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H05K1/11 ,  H01L23/00 ,  H05K3/42 ,  H05K3/46 ,  H05K1/03

CPC classification number: H01L23/481 ,  H01L23/49822 ,  H01L23/49816 ,  H01L21/486 ,  H01L21/76898 ,  H05K1/112 ,  H01L24/16 ,  H05K3/429 ,  H05K3/4644 ,  H05K1/0306 ,  H01L2224/16225

Abstract: In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.

公开(公告)号：US20240079339A1

公开(公告)日：2024-03-07

申请号：US17929045

申请日：2022-09-01

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Benjamin T. Duong ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L23/481 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate including a first integrated circuit (IC) die embedded therein; and a second IC die coupled to the package substrate and conductively coupled to the first IC die by vias in the package substrate. The package substrate has a first side and an opposing second side, the second IC die is coupled to the first side of the package substrate, the first IC die is between the first side of the package substrate and the second side of the package substrate, the package substrate comprises a plurality of layers of conductive traces in an organic dielectric material, the first IC die is surrounded by the organic dielectric material of the package substrate, the vias are in the organic dielectric material between the first IC die and the first side of the package substrate, and the first IC die comprises through-substrate vias.

公开(公告)号：US20230402368A1

公开(公告)日：2023-12-14

申请号：US17837732

申请日：2022-06-10

Applicant: Intel Corporation

Inventor： Benjamin T. Duong ,  Brian P. Balch ,  Kristof Darmawikarta ,  Darko Grujicic ,  Suddhasattwa Nad ,  Xing Sun ,  Marcel A. Wall ,  Yi Yang

IPC: H01L23/522 ,  H01C7/00 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L28/24 ,  H01L23/5226 ,  H01C7/006

Abstract: Techniques for thin-film resistors in vias are disclosed. In the illustrative embodiment, thin-film resistors are formed in through-glass vias of a glass substrate of an interposer. The thin-film resistors do not take up a significant amount of area on a layer of the interposer, as the thin-film resistor extends vertically through a via rather than horizontally on a layer of the interposer. The thin-film resistors may be used for any suitable purpose, such as power dissipation or voltage control, current control, as a pull-up or pull-down resistor, etc.

公开(公告)号：US20230395445A1

公开(公告)日：2023-12-07

申请号：US17833650

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Tarek A. Ibrahim ,  Jeremy D. Ecton ,  Brandon Christian Marin ,  Gang Duan ,  Suddhasattwa Nad ,  Yi Yang ,  Benjamin T. Duong ,  Junxin Wang ,  Sameer R. Paital

IPC: H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H05K1/03 ,  H05K3/40

CPC classification number: H01L23/15 ,  H01L23/49827 ,  H01L21/486 ,  H05K1/0306 ,  H05K3/4061

Abstract: In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.

公开(公告)号：US20230185033A1

公开(公告)日：2023-06-15

申请号：US17552169

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Benjamin T. Duong ,  Srinivas V. Pietambaram ,  Tarek A. Ibrahim ,  Ala Omer ,  Bai Nie ,  Hari Mahalingam

IPC: G02B6/42 ,  G02B6/43

CPC classification number: G02B6/4212 ,  G02B6/43 ,  G02B6/4239

Abstract: Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include an integrated circuit (IC) in a first layer, wherein the first layer includes a substrate having a first surface, an opposing second surface, and a lateral surface substantially perpendicular to the first and second surfaces, wherein the substrate includes a waveguide between the first and second surfaces, and wherein and the IC is nested in a cavity in the substrate; a PIC in a second layer, wherein the second layer is on the first layer and an active surface of the PIC faces the first layer, and wherein the IC is electrically coupled to the active side of the PIC; and an optical component optically coupled to the active surface of the PIC and the waveguide in the substrate at the second surface.