SEMICONDUCTOR DEVICE WITH RELEASED SOURCE AND DRAIN

    公开(公告)号:US20190172941A1

    公开(公告)日:2019-06-06

    申请号:US16304620

    申请日:2016-07-02

    Abstract: Embodiments are generally directed to a semiconductor device with released source and drain. An embodiment of a method includes etching a buffer layer of a semiconductor device to form a gate trench under a gate channel portion of a channel layer of the device; filling the gate trench with an oxide material to form an oxide isolation layer; etching one or more source/drain contact trenches in an interlayer dielectric (ILD) layer for source and drain regions of the device; etching the oxide isolation layer within the one or more source/drain contact trenches to form one or more cavities under a source/drain channel in the source and drain regions, wherein the etching of each contact trench is to expose all sides of the source/drain channel; and depositing contact metal in the one or more contact trenches, including depositing the contact metal in the cavities under the source/drain channel.

    FIN-BASED III-V/SI OR GE CMOS SAGE INTEGRATION

    公开(公告)号:US20180315757A1

    公开(公告)日:2018-11-01

    申请号:US15771080

    申请日:2015-12-22

    Abstract: Embodiments of the invention include a semiconductor structure and a method of making such a structure. In one embodiment, the semiconductor structure comprises a first fin and a second fin formed over a substrate. The first fin may comprise a first semiconductor material and the second fin may comprise a second semiconductor material. In an embodiment, a first cage structure is formed adjacent to the first fin, and a second cage structure is formed adjacent to the second fin. Additionally, embodiments may include a first gate electrode formed over the first fin, where the first cage structure directly contacts the first gate electrode, and a second gate electrode formed over the second fin, where the second cage structure directly contacts the second gate electrode.

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