公开(公告)号：US20180366587A1

公开(公告)日：2018-12-20

申请号：US15777117

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Kent E. MILLARD ,  Marc C. FRENCH ,  Ashish AGRAWAL ,  Benjamin CHU-KUNG ,  Ryan E. ARCH

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US20170288019A1

公开(公告)日：2017-10-05

申请号：US15626018

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Van H. LE ,  Ravi PILLARISETTY ,  Jessica S. KACHIAN ,  Marc C. FRENCH ,  Aaron A. BUDREVICH

IPC: H01L29/06

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696 ,  Y02E10/50

Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

公开(公告)号：US20170047401A1

公开(公告)日：2017-02-16

申请号：US15334112

申请日：2016-10-25

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Van H. LE ,  Ravi PILLARISETTY ,  Jessica S. KACHIAN ,  Marc C. FRENCH ,  Aaron A. BUDREVICH

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/167 ,  H01L29/66 ,  H01L29/165 ,  H01L29/51

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696 ,  Y02E10/50

Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

Abstract translation: 在那里制造的半导体器件堆叠和器件具有富锗器件层。 富锗器件层设置在衬底上方，其间布置有p型掺杂Ge蚀刻抑制层（例如，p型SiGe），以在去除牺牲半导体层期间抑制富锗器件层的蚀刻 Si比设备层更丰富。 随着在半导体膜堆叠中引入掩埋的p型掺杂半导体层，可以显着降低Ge在湿蚀刻剂（例如氢氧化物水溶液）中的溶解速率，从而提高蚀刻剂对Ge富集器件层的选择性。

公开(公告)号：US20210050455A1

公开(公告)日：2021-02-18

申请号：US17074251

申请日：2020-10-19

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Kent E. MILLARD ,  Marc C. FRENCH ,  Ashish AGRAWAL ,  Benjamin CHU-KUNG ,  Ryan E. ARCH

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/24 ,  H01L29/40 ,  H01L29/49

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US20200066515A1

公开(公告)日：2020-02-27

申请号：US16303125

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Van H. LE ,  Benjamin CHU-KUNG ,  Willy RACHMADY ,  Marc C. FRENCH ,  Seung Hoon SUNG ,  Jack T. KAVALIEROS ,  Matthew V. METZ ,  Ashish AGRAWAL

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.

公开(公告)号：US20180158933A1

公开(公告)日：2018-06-07

申请号：US15576468

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Ashish AGRAWAL ,  Matthew V. METZ ,  Willy RACHMADY ,  Marc C. FRENCH ,  Jack T. KAVALIEROS ,  Rafael RIOS ,  Seiyon KIM ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  James M. POWERS ,  Sherry R. TAFT

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.

公开(公告)号：US20170317187A1

公开(公告)日：2017-11-02

申请号：US15528793

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia RAHHAL-ORABI ,  Nancy M. ZELICK ,  Marc C. FRENCH ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L29/66742 ,  B82Y10/00 ,  H01L21/02392 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

Abstract: An embodiment includes a device comprising: first and second fins adjacent one another and each including channel and subfin layers, the channel layers having bottom surfaces directly contacting upper surfaces of the subfin layers; wherein (a) the bottom surfaces are generally coplanar with one another and are generally flat; (b) the upper surfaces are generally coplanar with one another and are generally flat; and (c) the channel layers include an upper material and the subfin layers include a lower III-V material different from the upper III-V material. Other embodiments are described herein.