公开(公告)号：US20210408288A1

公开(公告)日：2021-12-30

申请号：US16913835

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl NAYLOR ,  Chelsey DOROW ,  Kirby MAXEY ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Chia-Ching LIN ,  Sudarat LEE ,  Uygar E. AVCI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/24 ,  H01L29/66

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

公开(公告)号：US20240186416A1

公开(公告)日：2024-06-06

申请号：US18414290

申请日：2024-01-16

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl NAYLOR ,  Chelsey DOROW ,  Kirby MAXEY ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Chia-Ching LIN ,  Sudarat LEE ,  Uygar E. AVCI

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L21/02568 ,  H01L21/0262

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

公开(公告)号：US20240006481A1

公开(公告)日：2024-01-04

申请号：US17853547

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Chelsey DOROW ,  Kevin P. O'BRIEN ,  Sudarat LEE ,  Ande KITAMURA ,  Ashish Verma PENUMATCHA ,  Carl H. NAYLOR ,  Kirby MAXEY ,  Chia-Ching LIN ,  Scott B. CLENDENNING ,  Uygar E. AVCI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/78696

Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a source region, a drain region, a first semiconductor channel between the source region and the drain region, and a second semiconductor channel between the source region and the drain region over the first semiconductor channel. In an embodiment, an insulator is around the source region, the drain region, the first semiconductor channel, and the second semiconductor channel. In an embodiment, a first access hole is in the insulator adjacent to a first edge of the first semiconductor channel, and a second access hole is in the insulator adjacent to a second edge of the first semiconductor channel.

公开(公告)号：US20230317783A1

公开(公告)日：2023-10-05

申请号：US17709365

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Carl H. NAYLOR ,  Uygar E. AVCI ,  Chelsey DOROW ,  Kevin P. O'BRIEN ,  Scott B. CLENDENNING ,  Matthew V. METZ ,  Chia-Ching LIN ,  Sudarat LEE ,  Ashish Verma PENUMATCHA

IPC: H01L29/06 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823412 ,  H01L29/78651

Abstract: Embodiments described herein may be related to forming nano ribbon transistors using layered 2D semiconductor channels. The layered 2D semiconductor channels may be created by forming a scaffold structure that has a first edge that extends from a silicon-based substrate, and a second edge opposite the first edge that is distal to the silicon based substrate. Alternating layers of 2D semiconductor material and a 3D semiconductor material may then be built on the second edge of the scaffold structure. In embodiments, the 3D semiconductor material may then be removed and a gate material deposited around at least a portion of the layers of 2D semiconductor material.

公开(公告)号：US20230101604A1

公开(公告)日：2023-03-30

申请号：US17485314

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Tanay GOSAVI ,  Shriram SHIVARAMAN ,  Carl H. NAYLOR ,  Chelsey DOROW ,  Ian A. YOUNG ,  Nazila HARATIPOUR ,  Kevin P. O'BRIEN

IPC: H01L29/76 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L29/24

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to three-dimensional (3D) memory devices with transition metal dichalcogenide (TMD) channels. Other embodiments may be disclosed or claimed.

公开(公告)号：US20230098467A1

公开(公告)日：2023-03-30

申请号：US17485176

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Carl H. NAYLOR ,  Kirby MAXEY ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Uygar E. AVCI ,  Patrick THEOFANIS ,  Charles MOKHTARZADEH ,  Matthew V. METZ ,  Scott B. CLENDENNING

IPC: H01L27/092 ,  H01L29/24 ,  H01L29/06 ,  H01L29/423 ,  H01L29/76 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8256 ,  H01L29/66

Abstract: Thin film transistors having a spin-on two-dimensional (2D) channel material are described. In an example, an integrated circuit structure includes a first device layer including a first two-dimensional (2D) material layer above a substrate. The first 2D material layer includes molybdenum, sulfur, sodium and carbon. A second device layer including a second 2D material layer is above the substrate. The second 2D material layer includes tungsten, selenium, sodium and carbon.

公开(公告)号：US20230096347A1

公开(公告)日：2023-03-30

申请号：US17485202

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kevin P. O'BRIEN ,  Tristan A. TRONIC ,  Anandi ROY ,  Ashish Verma PENUMATCHA ,  Carl H. NAYLOR ,  Kirby MAXEY ,  Sudarat LEE ,  Chelsey DOROW ,  Scott B. CLENDENNING ,  Uygar E. AVCI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a sheet that is a semiconductor. In an embodiment a length dimension of the sheet and a width dimension of the sheet are greater than a thickness dimension of the sheet. In an embodiment, a gate structure is around the sheet, and a first spacer is adjacent to a first end of the gate structure, and a second spacer adjacent to a second end of the gate structure. In an embodiment, a source contact is around the sheet and adjacent to the first spacer, and a drain contact is around the sheet and adjacent to the second spacer.

公开(公告)号：US20230088101A1

公开(公告)日：2023-03-23

申请号：US17482232

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Carl H. NAYLOR ,  Kirby MAXEY ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Matthew V. METZ ,  Scott B. CLENDENNING

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Thin film transistors having edge-modulated two-dimensional (2D) channel material are described. In an example, an integrated circuit structure includes a device layer including a two-dimensional (2D) material layer above a substrate, the 2D material layer including a center portion and first and second edge portions, the center portion consisting essentially of molybdenum or tungsten and of sulfur or selenium, and the first and second edge portions including molybdenum or tungsten and including tellurium.

公开(公告)号：US20250113547A1

公开(公告)日：2025-04-03

申请号：US18375064

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Tao CHU ,  Chiao-Ti HUANG ,  Guowei XU ,  Robin CHAO ,  Feng ZHANG ,  Yue ZHONG ,  Yang ZHANG ,  Ting-Hsiang HUNG ,  Kevin P. O’BRIEN ,  Uygar E. AVCI ,  Carl H. NAYLOR ,  Mahmut Sami KAVRIK ,  Andrey VYATSKIKH ,  Rachel STEINHARDT ,  Chelsey DOROW ,  Kirby MAXEY

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775

Abstract: Integrated circuit structures having internal spacers for 2D channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2D channel materials, are described. For example, an integrated circuit structure includes a stack of two-dimensional (2D) material nanowires. A gate structure is vertically around the stack of 2D material nanowires. Internal gate spacers are between vertically adjacent ones of the stack of 2D material nanowires and laterally adjacent to the gate structure. The 2D material nanowires are recessed relative to the internal gate spacers. Conductive contact structures are at corresponding ends of the stack of 2D material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.

公开(公告)号：US20230113614A1

公开(公告)日：2023-04-13

申请号：US17485185

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kevin P. O'BRIEN ,  Chelsey DOROW ,  Carl NAYLOR ,  Kirby MAXEY ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Scott B. CLENDENNING ,  Urusa ALAAN ,  Tristan A. TRONIC

IPC: H01L29/423 ,  H01L29/786 ,  H01L27/12

Abstract: Thin film transistors having CMOS functionality integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a first device including a first two-dimensional (2D) material layer, and a first gate stack around the first 2D material layer. The first gate stack has a gate electrode around a gate dielectric layer. A second device is stacked on the first device. The second device includes a second 2D material layer, and a second gate stack around the second 2D material layer. The second gate stack has a gate electrode around a gate dielectric layer. The second 2D material layer has a composition different than a composition of the first 2D material layer.