公开(公告)号：US20230197574A1

公开(公告)日：2023-06-22

申请号：US18111329

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Aditya S. VAIDYA ,  Ravindranath V. MAHAJAN ,  Digvijay A. RAORANE ,  Paul R. START

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5385 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/09 ,  H01L24/83 ,  H01L25/16 ,  H01L25/0655 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16237

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US20210272881A1

公开(公告)日：2021-09-02

申请号：US17323840

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Aditya S. VAIDYA ,  Ravindranath V. MAHAJAN ,  Digvijay A. RAORANE ,  Paul R. START

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H01L25/065

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US20200075501A1

公开(公告)日：2020-03-05

申请号：US16070507

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Digvijay A. RAORANE ,  Vijay K. NAIR

IPC: H01L23/552 ,  H01L23/13 ,  H01L23/49 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

Abstract: Electromagnetic interference shielding is described for a semiconductor package using bond wires. In one example, a package has a substrate having a ground plane and a top side to carry a microelectronic die, the top side further having a conductive pad coupled to the ground plane, a microelectronic die having a bottom side attached to the substrate and a top side opposite the bottom side, and a plurality of bond wires connected to the top conductive pad to form a wire mesh electromagnetic interference shield for the substrate.

公开(公告)号：US20160088738A1

公开(公告)日：2016-03-24

申请号：US14956214

申请日：2015-12-01

Applicant: Intel Corporation

Inventor： Digvijay A. RAORANE ,  Kemal AYGUN ,  Daniel N. SOBIESKI ,  Drew W. DELANEY

IPC: H05K3/00 ,  H05K3/02 ,  H05K1/02 ,  H05K3/30

CPC classification number: H05K3/007 ,  C23C14/14 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/1815 ,  H01L2924/18162 ,  H05K1/0219 ,  H05K1/185 ,  H05K3/02 ,  H05K3/30 ,  H05K3/4682 ,  H05K2201/0715 ,  H05K2203/1469 ,  H05K2203/308 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/83005

Abstract: An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.