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    REFERENCE ARCHITECTURE IN A CROSS-POINT MEMORY
    11.
    发明申请
    REFERENCE ARCHITECTURE IN A CROSS-POINT MEMORY 有权
    跨点存储器中的参考架构

    公开(公告)号：US20160093375A1

    公开(公告)日：2016-03-31

    申请号：US14850152

    申请日：2015-09-10

    Applicant: Intel Corporation

    Inventor： Balaji Srinivasan ,  Doyle Rivers ,  Derchang Kau ,  Matthew Goldman

    IPC: G11C13/00

    CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C8/08 ,  G11C11/24 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/77

    Abstract: The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (VREF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on VREF and a detected memory cell voltage VLWL.

    Abstract translation: 本公开涉及交叉点存储器中的参考和感测架构。 设备可以包括被配置为选择用于存储器访问操作的目标存储器单元的存储器控​​制器。 存储器控制器包括被配置为选择与目标存储器单元相关联的全局WL（GWL）和本地WL（LWL）的字线（WL）开关电路; 配置为选择与目标存储器单元相关联的全局BL（GBL）和本地BL（LBL）的位线（BL）开关电路; 以及感测电路，包括第一感测电路电容和第二感测电路电容，所述感测电路经配置以将所选择的GWL，LWL和第一感测电路电容预充电至WL偏置电压WLVDM，产生利用电荷的参考电压（VREF） 在所选择的GWL上并对第一感测电路电容进行充电，并且至少部分地基于VREF和检测到的存储器单元电压VLWL来确定目标存储器单元的状态。

    Thermal monitoring of memory resources
    12.
    发明授权
    Thermal monitoring of memory resources 有权

    公开(公告)号：US10678315B2

    公开(公告)日：2020-06-09

    申请号：US16147950

    申请日：2018-10-01

    Applicant: Intel Corporation

    Inventor： Rajesh Sundaram ,  Muthukumar P. Swaminathan ,  Doyle Rivers

    IPC: G06F1/20 ,  G06F1/3234 ,  G06F1/3225

    Abstract: Data reliability and integrity may be compromised when memory resources used to store the data reach elevated temperatures. A sensor in the memory resource may monitor the temperature of the memory resource in real-time. A comparator in the memory resource may indicate a high temperature condition to a memory controller. The memory controller, in response to the high temperature condition, can restrict or halt data flow to the memory resource. When the real-time temperature of the memory resource falls below a defined threshold, the memory controller may resume data flow to the memory resource.

    Reference architecture in a cross-point memory
    17.
    发明授权
    Reference architecture in a cross-point memory 有权
    参考架构在交叉点内存中

    公开(公告)号：US09142271B1

    公开(公告)日：2015-09-22

    申请号：US14313695

    申请日：2014-06-24

    Applicant: Intel Corporation

    Inventor： Balaji Srinivasan ,  Doyle Rivers ,  Derchang Kau ,  Matthew Goldman

    IPC: G11C7/00 ,  G11C7/12

    CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C8/08 ,  G11C11/24 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/77

    Abstract: The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (VREF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on VREF and a detected memory cell voltage VLWL.

    Abstract translation: 本公开涉及交叉点存储器中的参考和感测架构。 设备可以包括被配置为选择用于存储器访问操作的目标存储器单元的存储器控​​制器。 存储器控制器包括被配置为选择与目标存储器单元相关联的全局WL（GWL）和本地WL（LWL）的字线（WL）开关电路; 配置为选择与目标存储器单元相关联的全局BL（GBL）和本地BL（LBL）的位线（BL）开关电路; 以及感测电路，包括第一感测电路电容和第二感测电路电容，所述感测电路经配置以将所选择的GWL，LWL和第一感测电路电容预充电至WL偏置电压WLVDM，产生利用电荷的参考电压（VREF） 在所选择的GWL上并对第一感测电路电容进行充电，并且至少部分地基于VREF和检测到的存储器单元电压VLWL来确定目标存储器单元的状态。

    Flexible identification technique
    18.
    发明授权
    Flexible identification technique 有权
    灵活的识别技术

    公开(公告)号：US08982661B2

    公开(公告)日：2015-03-17

    申请号：US13910632

    申请日：2013-06-05

    Applicant: Intel Corporation

    Inventor： Julie M. Walker ,  Doyle Rivers

    IPC: G11C8/00 ,  G11C8/04 ,  G11C5/14 ,  G11C8/06

    CPC classification number: G11C8/04 ,  G11C5/14 ,  G11C8/06 ,  G11C8/12 ,  G11C16/20

    Abstract: A shared-signaling multi-device memory system is capable of changing between addressing modes without the multi-device memory being required to undergo a power cycle. First and second registers of a memory device are set to both contain first address-identification information in response a first address-assignment command that is received a power cycle. The first register is set to contain second address-identification information in response a second address-assignment command that is received subsequently to the first address assignment command. Depending on the value of the second address-identification information, the memory device is configured in an individual-device-addressing mode or a parallel addressing mode without a power cycle. The first register can be reset to the first address-identification information contained in the second register in response to an address-restore command without a power cycle. A corresponding method is also disclosed.

    Abstract translation: 共享信令多设备存储器系统能够在寻址模式之间改变，而不需要多器件存储器来进行功率循环。 存储器件的第一和第二寄存器被设置为响应于接收到功率周期的第一地址分配命令而包含第一地址识别信息。 响应于在第一地址分配命令之后接收到的第二地址分配命令，将第一寄存器设置为包含第二地址识别信息。 取决于第二地址识别信息的值，存储器件被配置为单个设备寻址模式或并行寻址模式而没有功率循环。 响应于没有电源循环的地址恢复命令，第一寄存器可以被重置为包含在第二寄存器中的第一地址识别信息。 还公开了相应的方法。

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