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    Method and apparatus for processing sequential writes to a block group of physical blocks in a memory device
    11.
    发明授权
    Method and apparatus for processing sequential writes to a block group of physical blocks in a memory device 有权

    公开(公告)号：US10031845B2

    公开(公告)日：2018-07-24

    申请号：US15089315

    申请日：2016-04-01

    Applicant: INTEL CORPORATION

    Inventor： Frank T. Hady

    IPC: G06F12/00 ,  G06F12/02 ,  G06F13/00 ,  G06F13/28

    Abstract: Provided are an apparatus and method for processing sequential writes to a block group of physical blocks in a memory device. Sequential write data for a plurality of consecutive logical addresses is received and a determination is made of consecutive physical blocks comprising a block group. Each of the physical blocks has data for a plurality of the consecutive logical addresses. The sequential write data is written to consecutive physical data locations having data for the determined consecutive physical blocks of the block group. The block group metadata for the block group is updated.

    Managing disturbance induced errors
    15.
    发明授权
    Managing disturbance induced errors 有权
    管理扰动引起的错误

    公开(公告)号：US09202547B2

    公开(公告)日：2015-12-01

    申请号：US13832278

    申请日：2013-03-15

    Applicant: Intel Corporation

    Inventor： Prashant S. Damle ,  Frank T. Hady ,  Paul D. Ruby ,  Kiran Pangal ,  Sowmiya Jayachandran

    IPC: G06F12/16 ,  G11C11/406 ,  G11C16/34

    CPC classification number: G11C7/1072 ,  G11C11/406 ,  G11C11/40618 ,  G11C16/3431

    Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.

    Abstract translation: 在一个实施例中，存储器控制器可以确定与存储器件中的目标存储器单元相关联的一个或多个相邻存储器单元将被刷新。 控制器可以生成与刷新一个或多个相邻存储器单元相关联的命令。 控制器可以将命令从存储器控制器传送到包含目标存储器单元的存储器件。 命令可以指示存储器设备刷新相邻存储器单元和/或返回与相邻存储器单元相关联的一个或多个地址。

    PROGRAMMABLE WRITE FILTER HARDWARE
    18.
    发明申请
    PROGRAMMABLE WRITE FILTER HARDWARE 有权

    公开(公告)号：US20250123955A1

    公开(公告)日：2025-04-17

    申请号：US19001843

    申请日：2024-12-26

    Applicant: Intel Corporation

    Inventor： Frank T. Hady ,  Scott D. Peterson ,  Andrzej Stasiak

    IPC: G06F12/02 ,  G06F12/0815

    Abstract: Write filter hardware is provided with circuitry to receive a signal to switch the write filter from a disabled state to an enabled state for a given range of addresses in a shared memory. A write attempt by a host processor to the range of addresses is identified, where access to the shared memory is shared with an accelerator device. The write filter hardware causes the write attempt to be dropped when the hardware write filter is in the enabled state for the given range of addresses.

    Load reduced nonvolatile memory interface
    19.
    发明授权
    Load reduced nonvolatile memory interface 有权

    公开(公告)号：US11500795B2

    公开(公告)日：2022-11-15

    申请号：US16664535

    申请日：2019-10-25

    Applicant: Intel Corporation

    Inventor： Emily P. Chung ,  Frank T. Hady ,  George Vergis

    IPC: G06F13/42 ,  G06F13/16 ,  G06F13/40 ,  G11C11/4076 ,  G11C11/4093 ,  G11C16/32 ,  G11C7/10

    Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.

    Load reduced nonvolatile memory interface
    20.
    发明授权
    Load reduced nonvolatile memory interface 有权

    公开(公告)号：US10459855B2

    公开(公告)日：2019-10-29

    申请号：US15201370

    申请日：2016-07-01

    Applicant: Intel Corporation

    Inventor： Emily Chung ,  Frank T. Hady ,  George Vergis

    IPC: G06F13/42 ,  G06F13/16 ,  G06F13/40 ,  G11C11/4076 ,  G11C11/4093 ,  G11C7/10 ,  G11C16/32

    Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.

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