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    DISTRIBUTION OF ERROR CHECKING AND CORRECTION (ECC) BITS TO ALLOCATE ECC BITS FOR METADATA
    12.
    发明申请
    DISTRIBUTION OF ERROR CHECKING AND CORRECTION (ECC) BITS TO ALLOCATE ECC BITS FOR METADATA 有权

    公开(公告)号：US20210141692A1

    公开(公告)日：2021-05-13

    申请号：US17156399

    申请日：2021-01-22

    Applicant: Intel Corporation

    Inventor： Rajat AGARWAL ,  Wei P. CHEN ,  Bill NALE ,  James A. McCALL

    IPC: G06F11/10

    Abstract: A memory subsystem includes multiple memory resources connected in parallel, including a first memory resource and a second memory resource. The memory subsystem can split a portion of data into multiple sub-portions. Split into smaller portions, the system needs fewer ECC (error checking and correction) bits to provide the same level of ECC protection. The portion of data can include N ECC bits for error correction, and the sub-portions can each include a sub-portion of (N−M) ECC bits for error correction. The system can then use M bits of data for non-ECC purposes, such as metadata.

    IMPEDANCE COMPENSATION BASED ON DETECTING SENSOR DATA
    15.
    发明申请
    IMPEDANCE COMPENSATION BASED ON DETECTING SENSOR DATA 审中-公开

    公开(公告)号：US20190004919A1

    公开(公告)日：2019-01-03

    申请号：US15993245

    申请日：2018-05-30

    Applicant: Intel Corporation

    Inventor： James A. McCALL ,  Kuljit S. BAINS

    IPC: G06F11/30 ,  G11C29/50 ,  G11C29/02 ,  G11C7/10 ,  G06F13/42

    Abstract: A memory subsystem manages memory I/O impedance compensation by the memory device monitoring a need for impedance compensation. Instead of a memory controller regularly sending a signal to have the memory device update the impedance compensation when a change is not needed, the memory device can indicate when it is ready to perform an impedance compensation change. The memory controller can send an impedance compensation signal to the memory device in response to a compensation flag set by the memory or in response to determining that a sensor value has changed in excess of a threshold.

    CONNECTOR PINS FOR REDUCING CROSSTALK
    17.
    发明公开
    CONNECTOR PINS FOR REDUCING CROSSTALK 审中-公开

    公开(公告)号：US20240145996A1

    公开(公告)日：2024-05-02

    申请号：US18395069

    申请日：2023-12-22

    Applicant: Intel Corporation

    Inventor： Xiang LI ,  George VERGIS ,  James A. McCALL

    IPC: H01R13/6471 ,  H01R12/73

    CPC classification number: H01R13/6471 ,  H01R12/737

    Abstract: A new connector implemented with connector pins to reduce crosstalk significantly improves memory channel electrical performance for next generation DDR (double data rate) technology. To reduce crosstalk the connector pins include pins with three different pin shapes, including two differently shaped signal pins and a ground pin that combines the shapes of the signal pins. The shaped pins enables them to be positioned in a connector so that each signal pin can have its own independent and separate signal return path on a single ground pin. In this manner, crosstalk can be significantly reduced.

    DYNAMIC SWITCH FOR MEMORY DEVICES
    18.
    发明公开
    DYNAMIC SWITCH FOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20240028531A1

    公开(公告)日：2024-01-25

    申请号：US18375472

    申请日：2023-09-30

    Applicant: Intel Corporation

    Inventor： John R. DREW ,  James A. McCALL ,  Tongyan ZHAI ,  Jun LIAO ,  Min Suet LIM ,  Shigeki TOMISHIMA

    IPC: G06F13/16 ,  G06F13/40

    CPC classification number: G06F13/1694 ,  G06F13/1689 ,  G06F13/4022

    Abstract: A memory subsystem triggers dynamic switching for memory devices to provide access to active memory devices and prevent access to inactive memory devices. Dynamic switching enables a single bus to switch between multiple memory devices whose capacity otherwise exceeds the capacity of the single bus. A switch can be mounted in a memory module or directly on a motherboard alongside the memory devices. A memory controller can toggle a chip select signal as a single control signal to drive the switch. Each switch includes pairs of field effect transistors (FETs), including any of CMOS, NMOS and PMOS FETs. The switch electrically isolates inactive memory devices to prevent access without the need to electrically short the devices.

    BUFFER THAT SUPPORTS BURST TRANSFERS HAVING PARALLEL CRC AND DATA TRANSMISSIONS
    20.
    发明申请
    BUFFER THAT SUPPORTS BURST TRANSFERS HAVING PARALLEL CRC AND DATA TRANSMISSIONS 有权

    公开(公告)号：US20210279128A1

    公开(公告)日：2021-09-09

    申请号：US17327432

    申请日：2021-05-21

    Applicant: Intel Corporation

    Inventor： James A. McCALL ,  Bill NALE ,  Zibing YANG ,  Yanjie ZHU

    IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30

    Abstract: A method is described. The method includes a buffer semiconductor chip receiving a plurality of data signals. The method includes the buffer chip calculating first CRC information from the plurality of data signals. The method includes the buffer chip transmitting the plurality of data signals in parallel with the first CRC information if a read burst transfer sequence is being performed, the buffer chip receiving second CRC information in parallel with the plurality of data signals and comparing the first CRC information with the second CRC information if a write burst transfer sequence is being performed.

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