公开(公告)号：US10528463B2

公开(公告)日：2020-01-07

申请号：US15278837

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Peng Li ,  Anand S. Ramalingam ,  William K. Lui ,  Sanjeev N. Trika

IPC: G06F12/02 ,  G06F3/06 ,  G11C14/00

Abstract: Technologies for combining logical-to-physical address updates include a data storage device. The data storage device includes a non-volatile memory to store data and a logical to physical (L2P) table indicative of logical addresses and associated physical addresses of the data. Additionally, the data storage device includes a volatile memory to store one or more bins. Each bin is indicative of a subset of entries in the L2P table. Further, the data storage device includes a controller to allocate a bin in the volatile memory, write a plurality of updates to a subset of entries of the L2P table to the bin, and write the bin to the L2P table in a single write operation. Other embodiments are also described and claimed.

公开(公告)号：US20190303284A1

公开(公告)日：2019-10-03

申请号：US15939398

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Sanjeev Trika ,  Jawad Khan ,  Peng Li ,  Myron Loewen

IPC: G06F12/02 ,  G06F3/06 ,  G06F17/30 ,  G06F21/62

Abstract: An embodiment of a mass storage apparatus may include first non-volatile media, second non-volatile media which provides a relatively larger write granularity as compared to the first non-volatile media, and logic communicatively coupled to the first and second non-volatile media to direct an access request to one of the first non-volatile media and the second non-volatile media based on an indication from an operating system. An embodiment of a host computing apparatus may include a processor, memory communicatively coupled to the processor, and logic communicatively coupled to the processor to provide an indication for a file system-related access request to a mass storage device based on a granularity size for the file system-related access request. Other embodiments are disclosed and claimed.

公开(公告)号：US10430333B2

公开(公告)日：2019-10-01

申请号：US15721547

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Peng Li ,  Jawad B. Khan ,  Sanjeev N. Trika

IPC: G06F12/06 ,  G11C7/10 ,  G05B19/045

Abstract: An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.

公开(公告)号：US20190041594A1

公开(公告)日：2019-02-07

申请号：US15835177

申请日：2017-12-07

Applicant: Intel Corporation

Inventor： Peng Li ,  Joel Martinez ,  Jon Long

IPC: G02B6/43 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.

公开(公告)号：US20190005079A1

公开(公告)日：2019-01-03

申请号：US15639651

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Peng Li

IPC: G06F17/30

Abstract: Systems, apparatuses and methods may store data. A system may include a processor communicatively coupled to an indexing structure and a datastore log separate from the indexing structure. The indexing structure may store key data corresponding to a key of a key-value pair and an address for the key-value pair. The datastore log may store the key-value pair at the address in a logical band of a plurality of independent logical bands. In addition, the system may include a memory device coupled to the processor. The memory device may include instructions, which when executed by the processor, may cause the system to execute an operation involving the key-value pair.

公开(公告)号：US12094800B2

公开(公告)日：2024-09-17

申请号：US16721809

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Jin Yang ,  Chia-Pin Chiu ,  Peng Li ,  Deepak Goyal

IPC: H01L23/31 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/373 ,  H01L23/538

CPC classification number: H01L23/3675 ,  H01L23/3121 ,  H01L23/3185 ,  H01L25/0652 ,  H01L25/18 ,  H01L23/3731 ,  H01L23/3736 ,  H01L23/3738 ,  H01L23/538 ,  H01L24/32 ,  H01L2224/32225

Abstract: Embodiments include semiconductor packages. A semiconductor package includes first and second bottom dies on a package substrate, first top dies on the first bottom die, and second top dies on the second bottom die. The semiconductor package includes thermally conductive slugs on the first bottom die and the second bottom die. The thermally conductive slugs are comprised of a high thermal conductive material. The thermally conductive slugs are positioned directly on outer edges of top surfaces of the first and second bottom dies, inner edges of the top surfaces of the first and second bottom dies, and/or a top surface of the package substrate. The high thermal conductive material of the thermally conductive slugs is comprised of copper, silver, boron nitride, or graphene. The thermally conductive slugs may have two different thicknesses. The semiconductor package may include an active die and/or an integrated heat spreader with the pedestals.

公开(公告)号：US11681463B2

公开(公告)日：2023-06-20

申请号：US17350574

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Peng Li ,  Jawad B. Khan ,  Sanjeev N. Trika

IPC: G06F3/06 ,  G06F12/1081 ,  G06F12/1009

CPC classification number: G06F3/0658 ,  G06F3/064 ,  G06F3/0613 ,  G06F3/0679 ,  G06F12/1081 ,  G06F12/1009

Abstract: A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host's DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.

公开(公告)号：US11676873B2

公开(公告)日：2023-06-13

申请号：US16614765

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Dinesh Padmanabhan Ramalekshmi Thanu ,  Hemanth K. Dhavaleswarapu ,  Venkata Suresh Guthikonda ,  John J. Beatty ,  Yonghao An ,  Marco Aurelio Cartas Ayala ,  Luke J. Garner ,  Peng Li

IPC: H01L23/16 ,  H01L21/52 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/16 ,  H01L21/52 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5383 ,  H01L25/0655 ,  H01L25/165 ,  H01L24/32 ,  H01L24/48 ,  H01L25/18 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2924/19041 ,  H01L2924/19105

Abstract: Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.

公开(公告)号：US11670569B2

公开(公告)日：2023-06-06

申请号：US16437872

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Amitesh Saha ,  Marco Aurelio Cartas ,  Peng Li ,  Bamidele Daniel Falola

IPC: H01L23/42 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L23/42 ,  H01L23/3737 ,  H01L24/17 ,  H01L2924/15311

Abstract: Disclosed herein are channeled lids for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a die between a lid and a package substrate. A bottom surface of the lid may include a channel that at least partially overlaps the die.

公开(公告)号：US11573895B2

公开(公告)日：2023-02-07

申请号：US17220842

申请日：2021-04-01

Applicant: Intel Corporation

Inventor： Peng Li ,  Jawad B. Khan ,  Sanjeev N. Trika

IPC: G06F12/06 ,  G11C7/10 ,  G05B19/045 ,  G06F3/06

Abstract: An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.