公开(公告)号：US12093100B2

公开(公告)日：2024-09-17

申请号：US17033753

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Ankush Varma ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Nikethan Shivanand Baligar ,  Stephen Wang ,  Nilanjan Palit ,  Timothy Yee-Kwong Kam ,  Adwait Purandare ,  Ujjwal Gupta ,  Stanley Chen ,  Dorit Shapira ,  Shruthi Venugopal ,  Suresh Chemudupati ,  Rupal Parikh ,  Eric Dehaemer ,  Pavithra Sampath ,  Phani Kumar Kandula ,  Yogesh Bansal ,  Dean Mulla ,  Michael Tulanowski ,  Stephen Paul Haake ,  Andrew Herdrich ,  Ripan Das ,  Nazar Syed Haider ,  Aman Sewani

IPC: G06F1/28 ,  G06F1/30 ,  G06F13/20

CPC classification number: G06F1/28 ,  G06F1/30 ,  G06F13/20 ,  G06F2213/40

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US11372467B2

公开(公告)日：2022-06-28

申请号：US16914290

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Ahmed Abou-Alfotouh ,  Phani Kumar Kandula ,  Linda L. Hurd ,  Eric C. Samson ,  Srikrishnan Venkataraman

IPC: G06F1/32 ,  G06F1/3234

Abstract: A system includes multiple processors and a power controller. Each processor includes a throttling engine. The power controller is to, in response to a determination that a first power consumption level exceeds a first threshold, assert a critical signal to each throttling engine of the plurality of processors. Further, for each processor, the throttling engine of the processor is to perform a sequence of multiple throttling states while the critical signal is asserted by the power controller, where the sequence of multiple throttling states is performed according to a state machine of the throttling engine. Other embodiments are described and claimed.

公开(公告)号：US10108241B2

公开(公告)日：2018-10-23

申请号：US14486695

申请日：2014-09-15

Applicant: Intel Corporation

Inventor： Phani Kumar Kandula ,  Tessil Thomas

IPC: G06F1/32 ,  G06F9/50

Abstract: Described is an apparatus comprising: a plurality of system agents, at least one system agent including one or more queues; and logic to monitor the one or more queues in at least one system agent and to cause the plurality of system agents to block traffic after satisfaction of a criterion.

公开(公告)号：US09874910B2

公开(公告)日：2018-01-23

申请号：US14471572

申请日：2014-08-28

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Phani Kumar Kandula ,  Jayakrishna Guddeti ,  Chandra P. Joshi ,  Junaid F. Thaliyil ,  Pavithra Sampath

IPC: G06F1/24 ,  G06F13/42

CPC classification number: G06F1/24 ,  G06F13/4221 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/14 ,  Y02D10/151

Abstract: In an embodiment, a processor includes at least one core to initiate a hot reset, and a peripheral device that is coupled to a root complex fabric via through the root port via an peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge. The processor also includes a power control unit that includes reset logic to decouple the peripheral device from the root complex fabric responsive to initiation of the hot reset. After the peripheral device is decoupled from the root complex fabric, the reset logic is to assert a reset of the peripheral device while a first core of the at least one core is in operation. Other embodiments are described and claimed.

公开(公告)号：US20160062424A1

公开(公告)日：2016-03-03

申请号：US14471572

申请日：2014-08-28

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Phani Kumar Kandula ,  Jayakrishna Guddeti ,  Chandra P. Joshi ,  Junaid F. Thaliyil ,  Pavithra Sampath

IPC: G06F1/24 ,  G06F9/44 ,  G06F13/42

CPC classification number: G06F1/24 ,  G06F13/4221 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/14 ,  Y02D10/151

Abstract: In an embodiment, a processor includes at least one core to initiate a hot reset, and a peripheral device that is coupled to a root complex fabric via through the root port via an peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge. The processor also includes a power control unit that includes reset logic to decouple the peripheral device from the root complex fabric responsive to initiation of the hot reset. After the peripheral device is decoupled from the root complex fabric, the reset logic is to assert a reset of the peripheral device while a first core of the at least one core is in operation. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括至少一个核心来启动热复位，以及外围设备，其经由外部组件互连通过根端口与根组合架构耦合到片上系统架构（PCIE至OSF ）桥。 处理器还包括功率控制单元，其包括复位逻辑，以响应于热复位的启动来将外围设备与根复杂结构分离。 在外围设备与根复杂结构解耦之后，复位逻辑是在至少一个核心的第一核心正在运行时断言外围设备的复位。 描述和要求保护其他实施例。

公开(公告)号：US12135569B2

公开(公告)日：2024-11-05

申请号：US17133279

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Rodrigo De Oliveira Vivi ,  John Kelbert ,  David Lombard ,  Eric Moret ,  Mark Luckeroth ,  Brad Bittel ,  Phani Kumar Kandula

IPC: G05D23/19 ,  G05B15/02 ,  G06F9/48 ,  G06F9/50

Abstract: Methods, apparatus, systems, and articles of manufacture to reduce thermal fluctuations in semiconductor processors are disclosed. An apparatus includes a temperature analyzer to determine a current temperature of a processor. The apparatus further includes a controller to provide an idle workload to the processor to execute in response to the current temperature falling below a setback temperature.

公开(公告)号：US20230113953A1

公开(公告)日：2023-04-13

申请号：US17961524

申请日：2022-10-06

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Phani Kumar Kandula ,  Ali Ibrahim ,  Murali Ramadoss ,  Ankur Shah

IPC: G06F1/3234 ,  G06F1/3296 ,  G06F1/324

Abstract: In one embodiment, a system on a chip integrated circuit (SoC) is provided that includes graphics processing resources including one or more graphics processing cores a memory subsystem including a memory controller, a physical interface, and a memory device and circuitry to dynamically adjust a voltage and frequency of the memory subsystem based on a workload executed by the graphics processing resources.

公开(公告)号：US11543868B2

公开(公告)日：2023-01-03

申请号：US16898603

申请日：2020-06-11

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Robin A. Steinbrecher ,  Sandeep Ahuja ,  Michael Berktold ,  Timothy Y. Kam ,  Howard Chin ,  Phani Kumar Kandula ,  Krishnakanth V. Sistla

IPC: G06F1/20 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  G06F3/041 ,  G06F11/30 ,  G06F1/32 ,  G06F1/26

Abstract: In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.

公开(公告)号：US20220100247A1

公开(公告)日：2022-03-31

申请号：US17033753

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Ankush Varma ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Nikethan Shivanand Baligar ,  Stephen Wang ,  Nilanjan Palit ,  Timothy Kam ,  Adwait Purandare ,  Ujjwal Gupta ,  Stanley Chen ,  Dorit Shapira ,  Shruthi Venugopal ,  Suresh Chemudupati ,  Rupal Parikh ,  Eric Dehaemer ,  Pavithra Sampath ,  Phani Kumar Kandula ,  Yogesh Bansal ,  Dean Mulla ,  Michael Tulanowski ,  Stephen Haake ,  Andrew Herdrich ,  Ripan Das

IPC: G06F1/28 ,  G06F1/30 ,  G06F13/20

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US20160147291A1

公开(公告)日：2016-05-26

申请号：US14554384

申请日：2014-11-26

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Phani Kumar Kandula ,  Ramamurthy Krithivas ,  Howard Chin ,  Ian M. Steiner ,  Vivek Garg

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3296 ,  G06F1/206 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多芯片封装（MCP）的第一芯片。 第一芯片包括至少一个核心和第一芯片温度控制（TC）逻辑，以响应于第一芯片的第一芯片温度超过第一阈值的指示来在MCP的第二芯片处断言第一功率调整信号。 处理器还包括导管，其包括将第一芯片耦合到MCP内的第二芯片的双向引脚。 导管将第一功率调整信号从第一芯片传输到第二芯片，第一功率调整信号将引起第二芯片的第二芯片功率消耗的调整。 描述和要求保护其他实施例。