公开(公告)号：US20190102170A1

公开(公告)日：2019-04-04

申请号：US16146430

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Gregory K. CHEN ,  Raghavan KUMAR ,  Huseyin Ekin SUMBUL ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Ian A. YOUNG

IPC: G06F9/30 ,  G06F9/38 ,  G11C11/419 ,  G11C13/00

Abstract: A compute-in-memory (CIM) circuit that enables a multiply-accumulate (MAC) operation based on a current-sensing readout technique. An operational amplifier coupled with a bitline of a column of bitcells included in a memory array of the CIM circuit to cause the bitcells to act like ideal current sources for use in determining an analog voltage value outputted from the operational amplifier for given states stored in the bitcells and for given input activations for the bitcells. The analog voltage value sensed by processing circuitry of the CIM circuit and converted to a digital value to compute a multiply-accumulate (MAC) value.

公开(公告)号：US20190042160A1

公开(公告)日：2019-02-07

申请号：US16147024

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Raghavan KUMAR ,  Phil KNAG ,  Gregory K. CHEN ,  Huseyin Ekin SUMBUL ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Ram KRISHNAMURTHY ,  Ian A. YOUNG

IPC: G06F3/06 ,  G04F10/00 ,  G11C11/419 ,  G11C13/00 ,  G11C11/418

Abstract: A memory circuit has compute-in-memory (CIM) circuitry that performs computations based on time-to-digital conversion (TDC). The memory circuit includes an array of memory cells addressable with column address and row address. The memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value. A processing circuit determines a value of the multiple memory cells based on the digital value.

公开(公告)号：US20250007688A1

公开(公告)日：2025-01-02

申请号：US18217561

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Raghavan KUMAR ,  Sanu K. MATHEW ,  Sachin TANEJA ,  Christopher B. WILKERSON ,  Minxuan ZHOU

IPC: H04L9/00 ,  G06F17/14 ,  H04L9/30

Abstract: A reconfigurable compute circuitry to perform Fully Homomorphic Encryption (FHE) enables a full utilization of compute resources and data movement resources by mapping multiple N*1024 polynomials on to a (M*N)*1024 polynomial. To counteract the shuffling of the coefficients during Number-Theoretic-Transforms (NTT) and inverse-NTT operations, compute elements in the compute circuitry operate in a bypass mode that is enabled by a data movement instruction, to convert from the shuffled form to contiguous form without modifying the values of the coefficients.

公开(公告)号：US20250005102A1

公开(公告)日：2025-01-02

申请号：US18599931

申请日：2024-03-08

Applicant: Intel Corporation

Inventor： Sachin TANEJA ,  Sanu K. MATHEW ,  Raghavan KUMAR ,  Nojan SHEYBANI ,  Vikram B. SURESH

IPC: G06F17/15 ,  H04L9/00

Abstract: Examples include techniques for twiddle factor generation for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations by a compute element. The compute element can be included in a parallel processing device. Examples include receiving information to generate a twiddle factor for use by the compute element to execute an NTT or an iNTT computation for an N-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.

公开(公告)号：US20230401434A1

公开(公告)日：2023-12-14

申请号：US18237887

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Ram KRISHNAMURTHY ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL

IPC: G06N3/063 ,  G06F7/523 ,  G06F9/38 ,  G06F9/30 ,  G06F7/509 ,  G06F7/544

CPC classification number: G06N3/063 ,  G06F7/523 ,  G06F9/3893 ,  G06F9/30098 ,  G06F7/5095 ,  G06F7/5443

Abstract: An apparatus is described. The apparatus includes a long short term memory (LSTM) circuit having a multiply accumulate circuit (MAC). The MAC circuit has circuitry to rely on a stored product term rather than explicitly perform a multiplication operation to determine the product term if an accumulation of differences between consecutive, preceding input values has not reached a threshold.

公开(公告)号：US20190138893A1

公开(公告)日：2019-05-09

申请号：US16147176

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Uygar AVCI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL ,  Nazila HARATIPOUR ,  Van H. LE

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US20190102359A1

公开(公告)日：2019-04-04

申请号：US16147036

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Phil KNAG ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Huseyin Ekin SUMBUL ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram A. Krishnamurthy ,  Ian A. Young

IPC: G06F17/16 ,  G11C11/419 ,  G11C11/418 ,  G11C7/10 ,  G06F9/30 ,  G11C11/56

Abstract: A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.

公开(公告)号：US20190042199A1

公开(公告)日：2019-02-07

申请号：US16147004

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin SUMBUL ,  Phil KNAG ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Abhishek SHARMA ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Ram KRISHNAMURTHY ,  Ian A. YOUNG

IPC: G06F7/544 ,  G11C8/10 ,  G11C7/12 ,  G11C8/08 ,  G06N3/08

Abstract: Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.

公开(公告)号：US20180181861A1

公开(公告)日：2018-06-28

申请号：US15392407

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Huseyin E. SUMBUL ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Phil C. Knag ,  Ram Krishnamurthy

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/088

Abstract: A neuromorphic computing system is provided which comprises: a synapse core; and a pre-synaptic neuron, a first post-synaptic neuron, and a second post-synaptic neuron coupled to the synaptic core, wherein the synapse core is to: receive a request from the pre-synaptic neuron, generate, in response to the request, a first address of the first post-synaptic neuron and a second address of the second post-synaptic neuron, wherein the first address and the second address are not stored in the synapse core prior to receiving the request.

公开(公告)号：US20250007687A1

公开(公告)日：2025-01-02

申请号：US18217551

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Sanu MATHEW ,  Vikram SURESH ,  Sachin TANEJA ,  Raghavan KUMAR ,  Christopher WILKERSON

IPC: H04L9/00

Abstract: Techniques for fully homomorphic encryption are described. In some examples, a register file to store polynomials is coupled to a butterfly compute path. The butterfly compute path includes a multiplier coupled to a first input and a second input to multiply the first and second input to, when enabled, generate a multiplication output, a first multiplexer coupled to an output of the multiplier and to the first input to output a selection between the output of the multiplier and the first input, an adder to add, when enabled, a third input to the selected output of the first multiplexer, a subtractor to subtract, when enabled, an output of the multiplier from the third input, and a second multiplexer coupled to an output of the multiplier and to the first input to, when enabled, output a selection between the output of the multiplier and the subtractor.