Abstract:
An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).
Abstract:
Disclosed is an N:1 (where N is an integer such as 3 or higher) resonant star topology converter to generate an input supply (e.g., 1.8V) for a processor (e.g., a system-on-chip (SOC)) from a higher power supply source (e.g., 12.6V) such as a battery or other source. The resonant star topology based regulator can be realized by a combination of on-die and on-package components as opposed to voltage regulators on motherboard with discrete inductor and capacitors. In one example, capacitors of the N:1 resonant star topology are implemented as multilayer ceramic capacitors (MLCC). The architecture of the N:1 resonant star topology based regulator results in high bandwidth. For example, compared to traditional step-down voltage regulators, the N:1 resonant star topology based regulator exhibits ten times higher bandwidth.
Abstract:
Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.
Abstract:
Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).
Abstract:
In some embodiments, a voltage regulator device may include a switched capacitor voltage regulator to receive an input voltage and to provide an output voltage to a load, and a control unit to receive information related to a desired output voltage for the switched capacitor voltage regulator and to determine a desired input voltage for the switched capacitor voltage regulator based on the desired output voltage and selected operation mode or modes of switched capacitor voltage regulator. Other embodiments are disclosed and claimed.