公开(公告)号：US20170011779A1

公开(公告)日：2017-01-12

申请号：US15206999

申请日：2016-07-11

Applicant: Intel Corporation

Inventor： Guido Droege ,  Andre Schaefer ,  Uwe Zillmann

IPC: G11C5/14

CPC classification number: H02J1/00 ,  G05F1/618 ,  G11C5/025 ,  G11C5/14 ,  G11C5/147 ,  G11C7/00 ,  H01L2924/19042 ,  H01L2924/19104 ,  H02M1/088

Abstract: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.

Abstract translation: 诸如异种装置的装置至少包括第一模具和第二模具。 该装置还包括第一电感元件，第二电感元件和开关控制电路。 开关控制电路设置在第一管芯中。 开关控制电路控制通过第一电感元件的电流以产生第一电压。 第一个电压为第一个模具供电。 第二电感元件耦合到第一电感元件。 第二电感元件产生第二电压以对第二管芯供电。 第一模具和第二模具可以根据不同的技术制造，并且其中第一模具和第二模具耐受不同的最大电压。 第一电压的大小可以大于第二电压的幅度。

公开(公告)号：US10290598B2

公开(公告)日：2019-05-14

申请号：US15323521

申请日：2014-08-07

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Ruchir Saraswat ,  Uwe Zillmann ,  Nicholas P. Cowley ,  Richard J. Goldman

IPC: H01L23/00 ,  H01F27/28 ,  G06F1/16 ,  H01L23/64 ,  H01L23/522 ,  H03H9/64 ,  H03H7/42 ,  H01L23/48 ,  H01L23/66 ,  H01L23/525

Abstract: Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on the backside, the one or more passive planar devices formed in the RDL.

公开(公告)号：US09881990B2

公开(公告)日：2018-01-30

申请号：US15169665

申请日：2016-05-31

Applicant: INTEL CORPORATION

Inventor： Andreas Duevel ,  Telesphor Kamgaing ,  Valluri R. Rao ,  Uwe Zillmann

IPC: H01F5/00 ,  H01F27/06 ,  G09G5/00 ,  H01L49/02 ,  H01F7/08 ,  H01L23/48 ,  H01L23/522 ,  H01F17/00 ,  H01L21/768 ,  H01L27/06 ,  H01L27/08

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F2017/002 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/08 ,  H01L2224/4813 ,  H01L2924/0002 ,  H01L2924/00012

Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.

公开(公告)号：US20170245035A1

公开(公告)日：2017-08-24

申请号：US15502495

申请日：2014-09-17

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Ruchir Saraswat ,  Uwe Zillmann ,  Valluri Bob Rao ,  Tor Lund-Larsen ,  Nicholas P. Cowley

IPC: H04R1/04 ,  H01L23/48 ,  H04R19/04 ,  B81C1/00 ,  H04R1/40 ,  H04R19/00 ,  B81B7/02 ,  H01L21/768

CPC classification number: H04R1/04 ,  B81B7/02 ,  B81B2201/0257 ,  B81B2207/096 ,  B81C1/00158 ,  B81C2201/0132 ,  B81C2203/0109 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/27002 ,  H01L2224/27618 ,  H01L2224/27848 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/3201 ,  H01L2224/32058 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/83005 ,  H01L2224/83193 ,  H01L2224/83438 ,  H01L2224/8346 ,  H01L2224/83488 ,  H01L2224/8359 ,  H01L2224/83688 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/92225 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/161 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/163 ,  H01L2924/166 ,  H04R1/406 ,  H04R19/005 ,  H04R19/04 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2221/68304

Abstract: Embodiments of the present disclosure describe a die with integrated microphone device using through-silicon vias (TSVs) and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a semiconductor substrate having a first side and a second side disposed opposite to the first side, an interconnect layer formed on the first side of the semiconductor substrate, a through-silicon via (TSV) formed through the semiconductor substrate and configured to route electrical signals between the first side of the semiconductor substrate and the second side of the semiconductor substrate, and a microphone device formed on the second side of the semiconductor substrate and electrically coupled with the TSV. Other embodiments may be described and/or claimed.

公开(公告)号：US10403511B2

公开(公告)日：2019-09-03

申请号：US13740428

申请日：2013-01-14

Applicant: Intel Corporation

Inventor： Ruchir Saraswat ,  Nicholas P. Cowley ,  Uwe Zillmann

IPC: H01Q1/38 ,  H01L21/48 ,  H01L23/48 ,  H01L23/522 ,  H01Q1/22 ,  H01L23/66 ,  H01Q21/06

Abstract: A patch antenna system comprising: an integrated circuit die having an active side including an active layer, and a backside; a dielectric layer formed on the backside; and a redistribution layer formed on the dielectric layer wherein the redistribution layer forms an array of patches. The patch antenna further comprises a plurality of through-silicon vias (TSV), wherein the TSVs electrically connect the array of patches to the active layer.

公开(公告)号：US10079489B2

公开(公告)日：2018-09-18

申请号：US15206999

申请日：2016-07-11

Applicant: Intel Corporation

Inventor： Guido Droege ,  Andre Schaefer ,  Uwe Zillmann

IPC: H02J1/00 ,  G11C7/00 ,  H02M1/088 ,  G11C5/14 ,  G11C5/02 ,  G05F1/618

CPC classification number: H02J1/00 ,  G05F1/618 ,  G11C5/025 ,  G11C5/14 ,  G11C5/147 ,  G11C7/00 ,  H01L2924/19042 ,  H01L2924/19104 ,  H02M1/088

Abstract: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.

公开(公告)号：US09287196B2

公开(公告)日：2016-03-15

申请号：US13730331

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Ruchir Saraswat ,  Uwe Zillmann ,  Andre Schaefer ,  Tor Lund-Larsen

IPC: H01L27/08 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065 ,  H01L27/06 ,  H01L23/64

CPC classification number: H01L23/481 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2223/6616 ,  H01L2223/6666 ,  H01L2223/6672 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Resonant clocking for three-dimensional stacked devices. An embodiment of an apparatus includes a stack including integrated circuit dies; and through silicon vias through at least one of the dies, wherein at least a first through silicon via of the through silicon vias includes a capacitive structure or an inductive structure, the first through silicon via being formed in a first die of the plurality of dies. The apparatus includes a resonant circuit, the first through silicon via used as a first circuit element of the resonant circuit.

Abstract translation: 谐振时钟三维堆叠器件。 装置的实施例包括：堆叠，其包括集成电路管芯; 并且通过至少一个管芯的硅通孔，其中穿过硅通孔的至少第一通孔硅通道包括电容结构或电感结构，所述第一穿硅通孔形成在所述多个管芯的第一管芯中 。 该装置包括谐振电路，第一通孔硅用作谐振电路的第一电路元件。

公开(公告)号：US11037896B2

公开(公告)日：2021-06-15

申请号：US16216881

申请日：2018-12-11

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Ruchir Saraswat ,  Uwe Zillmann ,  Nicholas P. Cowley ,  Richard J. Goldman

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/66 ,  G06F1/16 ,  H01F27/28 ,  H01L23/64 ,  H03H7/42 ,  H03H9/64 ,  H01L23/525

Abstract: Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on the backside, the one or more passive planar devices formed in the RDL.

公开(公告)号：US10455308B2

公开(公告)日：2019-10-22

申请号：US15502495

申请日：2014-09-17

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Ruchir Saraswat ,  Uwe Zillmann ,  Valluri Bob Rao ,  Tor Lund-Larsen ,  Nicholas P. Cowley

IPC: H04R19/04 ,  H04R1/04 ,  B81B7/02 ,  H01L23/00 ,  H01L21/683 ,  H01L23/48 ,  B81C1/00 ,  H01L21/768 ,  H04R1/40 ,  H04R19/00

Abstract: Embodiments of the present disclosure describe a die with integrated microphone device using through-silicon vias (TSVs) and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a semiconductor substrate having a first side and a second side disposed opposite to the first side, an interconnect layer formed on the first side of the semiconductor substrate, a through-silicon via (TSV) formed through the semiconductor substrate and configured to route electrical signals between the first side of the semiconductor substrate and the second side of the semiconductor substrate, and a microphone device formed on the second side of the semiconductor substrate and electrically coupled with the TSV. Other embodiments may be described and/or claimed.

公开(公告)号：US10256286B2

公开(公告)日：2019-04-09

申请号：US15589981

申请日：2017-05-08

Applicant: INTEL CORPORATION

Inventor： Andreas Duevel ,  Telesphor Kamgaing ,  Valluri R. Rao ,  Uwe Zillmann

IPC: H01F5/00 ,  H01F27/06 ,  G09G5/00 ,  H01L49/02 ,  H01F7/06 ,  H01L23/48 ,  H01L23/522 ,  H01F17/00 ,  H01L21/768 ,  H01L27/06 ,  H01L27/08

Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.