公开(公告)号：US10204794B2

公开(公告)日：2019-02-12

申请号：US15036351

申请日：2013-12-23

Applicant: Intel Corporation

Inventor： Muralidhar S. Ambati ,  Ritesh Jhaveri ,  Moosung Kim

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/324 ,  H01L29/06 ,  H01L29/66

Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

公开(公告)号：US12131912B2

公开(公告)日：2024-10-29

申请号：US18531359

申请日：2023-12-06

Applicant: Intel Corporation

Inventor： Muralidhar S. Ambati ,  Ritesh Jhaveri ,  Moosung Kim

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/324 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/66795

Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

公开(公告)号：US12094881B2

公开(公告)日：2024-09-17

申请号：US18108526

申请日：2023-02-10

Applicant: Intel Corporation

Inventor： Anand Murthy ,  Ryan Keech ,  Nicholas G. Minutillo ,  Ritesh Jhaveri

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823871 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/785 ,  H01L2029/7858

Abstract: Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm3 to about 5E21 atoms per cm3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon). The use of a layer having a high arsenic concentration can provide improved NMOS performance in the form of abrupt junctions in the source/drain regions and highly conductive source/drain regions with negligible diffusion of arsenic into the channel region.

公开(公告)号：US20230197729A1

公开(公告)日：2023-06-22

申请号：US18108526

申请日：2023-02-10

Applicant: Intel Corporation

Inventor： Anand Murthy ,  Ryan Keech ,  Nicholas G. Minutillo ,  Ritesh Jhaveri

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L29/167 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L29/66545 ,  H01L29/518 ,  H01L29/785 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/167 ,  H01L21/823871 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/1037 ,  H01L2029/7858

Abstract: Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm3 to about 5E21 atoms per cm3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon). The use of a layer having a high arsenic concentration can provide improved NMOS performance in the form of abrupt junctions in the source/drain regions and highly conductive source/drain regions with negligible diffusion of arsenic into the channel region.

公开(公告)号：US09406547B2

公开(公告)日：2016-08-02

申请号：US14139964

申请日：2013-12-24

Applicant: INTEL CORPORATION

Inventor： Ritesh Jhaveri ,  Jeanne L. Luce ,  Sang-Won Park ,  Dennis G. Hanken

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/02345 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids. After curing, the resultant dielectric layer can undergo wet chemical, thermal, and/or plasma treatment, for instance, to modify at least one of its dielectric properties, density, and/or etch rate.

Abstract translation: 公开了用于使用可流动介电材料提供半导体翅片的沟槽隔离的技术。 根据一些实施例，可流动电介质可以例如使用可流动的化学气相沉积（FCVD）工艺沉积在鳍状图案化的半导体衬底上。 可流动电介质可以流入相邻散热片之间的沟槽，其中它可以原位固化，从而根据一些实施例在衬底上形成电介质层。 通过固化，可以根据给定目标应用或最终用途的需要将可流动电介质转化为例如氧化物，氮化物和/或碳化物。 在一些实施例中，所得到的电介质层可以是基本上无缺陷的，没有或以其他方式减少接缝/空隙的量。 在固化之后，所得到的介电层可进行湿化学，热和/或等离子体处理，例如改变其介电特性，密度和/或蚀刻速率中的至少一个。