公开(公告)号：US20190034203A1

公开(公告)日：2019-01-31

申请号：US15665212

申请日：2017-07-31

Applicant: INTEL CORPORATION

Inventor： Federico Ardanaz ,  Roger Gramunt ,  Jesus Corbal ,  Dennis R. Bradford ,  Jonathan M. Eastep

IPC: G06F9/30 ,  G05F1/10 ,  G06F1/32 ,  G06F9/38

Abstract: An apparatus is provided which comprises: a component; a voltage generator to supply load current to the component; first one or more circuitries to predict that the load current is to increase from a first time; and second one or more circuitries to, in anticipation of the increase in the load current from the first time, cause the component to execute first instructions during a time period that occurs prior to the first time.

公开(公告)号：US09886396B2

公开(公告)日：2018-02-06

申请号：US14581285

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Roger Gramunt ,  Rammohan Padmanabhan ,  Ramon Matas ,  Neal S. Moyer ,  Benjamin C. Chaffin ,  Avinash Sodani ,  Alexey P. Suprun ,  Vikram S. Sundaram ,  Chung-Lun Chan ,  Gerardo A. Fernandez ,  Julio Gago ,  Michael S. Yang ,  Aditya Kesiraju

IPC: G06F9/30 ,  G06F9/44 ,  G06F12/12 ,  G06F12/122 ,  G06F9/48 ,  G06F9/38

CPC classification number: G06F12/122 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/4806 ,  G06F2212/62

Abstract: In one embodiment, a processor includes a frontend unit having an instruction decoder to receive and to decode instructions of a plurality of threads, an execution unit coupled to the instruction decoder to receive and execute the decoded instructions, and an instruction retirement unit having a retirement logic to receive the instructions from the execution unit and to retire the instructions associated with one or more of the threads that have an instruction or an event pending to be retired. The instruction retirement unit includes a thread arbitration logic to select one of the threads at a time and to dispatch the selected thread to the retirement logic for retirement processing.

公开(公告)号：US09715432B2

公开(公告)日：2017-07-25

申请号：US14581859

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Ramon Matas ,  Roger Gramunt ,  Chung-Lun Chan ,  Benjamin C. Chaffin ,  Aditya Kesiraju ,  Jonathan C. Hall ,  Jesus Corbal

IPC: G06F11/14 ,  G06F9/38

CPC classification number: G06F11/141 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/38 ,  G06F9/3859 ,  G06F9/3865

Abstract: Exemplary aspects are directed toward resolving fault suppression in hardware, which at the same time does not incur a performance hit. For example, when multiple instructions are executing simultaneously, a mask can specify which elements need not be executed. If the mask is disabled, those elements do not need to be executed. A determination is then made as to whether a fault happens in one of the elements that have been disabled. If there is a fault in one of the elements that has been disabled, a state machine re-fetches the instructions in a special mode. More specifically, the state machine determines if the fault is on a disabled element, and if the fault is on a disabled element, then the state machine specifies that the fault should be ignored. If during the first execution there was no mask, if there is an error present during execution, then the element is re-run with the mask to see if the error is a “real” fault.

公开(公告)号：US11334796B2

公开(公告)日：2022-05-17

申请号：US16983107

申请日：2020-08-03

Applicant: Intel Corporation

Inventor： Dipankar Das ,  Roger Gramunt ,  Mikhail Smelyanskiy ,  Jesus Corbal ,  Dheevatsa Mudigere ,  Naveen K. Mellempudi ,  Alexander F. Heinecke

IPC: G06F17/16 ,  G06F9/30 ,  G06F9/38 ,  G06F7/544 ,  G06N3/08 ,  G06N3/063 ,  G06N3/04

Abstract: A processing cluster of a processing cluster array comprises a plurality of registers to store input values of vector input operands, the input values of at least some of the vector input operands having different bit lengths than those of other input values of other vector input operands, and a compute unit to execute a dot-product instruction with the vector input operands to perform a number of parallel multiply operations and an accumulate operation per 32-bit lane based on a bit length of the smallest-sized input value of a first vector input operand relative to the 32-bit lane.

公开(公告)号：US10719320B2

公开(公告)日：2020-07-21

申请号：US15665212

申请日：2017-07-31

Applicant: INTEL CORPORATION

Inventor： Federico Ardanaz ,  Roger Gramunt ,  Jesus Corbal ,  Dennis R. Bradford ,  Jonathan M. Eastep

IPC: G06F1/32 ,  G06F9/30 ,  G05F1/10 ,  G06F1/3234 ,  G06F9/38 ,  G06F1/3206 ,  G06F1/30 ,  G06F1/26

Abstract: An apparatus is provided which comprises: a component; a voltage generator to supply load current to the component; first one or more circuitries to predict that the load current is to increase from a first time; and second one or more circuitries to, in anticipation of the increase in the load current from the first time, cause the component to execute first instructions during a time period that occurs prior to the first time.

公开(公告)号：US10445245B2

公开(公告)日：2019-10-15

申请号：US15384067

申请日：2016-12-19

Applicant: Intel Corporation

Inventor： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/14 ,  G06F12/0864

Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

公开(公告)号：US10445244B2

公开(公告)日：2019-10-15

申请号：US15384054

申请日：2016-12-19

Applicant: Intel Corporation

Inventor： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/14 ,  G06F12/0864

Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

公开(公告)号：US10007620B2

公开(公告)日：2018-06-26

申请号：US15282841

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Seth H. Pugsley ,  Christopher B. Wilkerson ,  Roger Gramunt ,  Jonathan C. Hall ,  Prabhat Jain

IPC: G06F12/00 ,  G06F12/121 ,  G06F12/0864 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0862

CPC classification number: G06F12/126 ,  G06F1/3275 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/70 ,  Y02D10/14

Abstract: A processor includes a set associative cache and a cache controller. The cache controller makes an initial association between first and second groups of sampled sets in the cache and first and second cache replacement policies. Follower sets in the cache are initially associated with the more conservative of the two policies. Following cache line insertions in a first epoch, the associations between the groups of sampled sets and cache replacement policies are swapped for the next epoch. If the less conservative policy outperforms the more conservative policy during two consecutive epochs, the follower sets are associated with the less conservative policy for the next epoch. Subsequently, if the more conservative policy outperforms the less conservative policy during any epoch, the follower sets are again associated with the more conservative policy. Performance may be measured based the number of cache misses associated with each policy.

公开(公告)号：US20180095895A1

公开(公告)日：2018-04-05

申请号：US15282841

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Seth H. Pugsley ,  Christopher B. Wilkerson ,  Roger Gramunt ,  Jonathan C. Hall ,  Prabhat Jain

IPC: G06F12/121 ,  G06F12/0864

CPC classification number: G06F12/121 ,  G06F1/3275 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/1021 ,  G06F2212/1028 ,  G06F2212/6042 ,  G06F2212/69 ,  G06F2212/70

Abstract: A processor includes a set associative cache and a cache controller. The cache controller makes an initial association between first and second groups of sampled sets in the cache and first and second cache replacement policies. Follower sets in the cache are initially associated with the more conservative of the two policies. Following cache line insertions in a first epoch, the associations between the groups of sampled sets and cache replacement policies are swapped for the next epoch. If the less conservative policy outperforms the more conservative policy during two consecutive epochs, the follower sets are associated with the less conservative policy for the next epoch. Subsequently, if the more conservative policy outperforms the less conservative policy during any epoch, the follower sets are again associated with the more conservative policy. Performance may be measured based the number of cache misses associated with each policy.

公开(公告)号：US09934155B2

公开(公告)日：2018-04-03

申请号：US13722485

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

IPC: G06F12/10 ,  G06F12/14 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/109

CPC classification number: G06F12/1009 ,  G06F12/0864 ,  G06F12/1027 ,  G06F12/109 ,  G06F12/145 ,  G06F2212/152 ,  G06F2212/6032 ,  G06F2212/652 ,  G06F2212/657 ,  G06F2212/68

Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.