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公开(公告)号：US09098415B2
公开(公告)日：2015-08-04
申请号：US13691016
申请日：2012-11-30
Applicant: Intel Corporation
Inventor： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
CPC classification number: G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。
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公开(公告)号：US20150149683A9
公开(公告)日：2015-05-28
申请号：US13691016
申请日：2012-11-30
Applicant: Intel Corporation
Inventor： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC: G06F13/40
CPC classification number: G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。
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13.发明授权公开(公告)号：US11615031B2
公开(公告)日：2023-03-28
申请号：US17498264
申请日：2021-10-11
Applicant: Intel Corporation
Inventor： Scott Dion Rodgers , Robert S. Chappell , Barry E. Huntley
IPC: G06F12/1009 , G06F12/1027 , G06F12/14
Abstract: An apparatus and method for managing different page tables for different privilege levels. For example, one embodiment of a processor comprises: a first control register to store a first base address associated with program code executed at a first privilege level; a second control register to store a second base address associated with program code executed at a second privilege level lower than the first privilege level; and address translation circuitry to identify a first base translation table using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level.
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14.发明授权公开(公告)号：US11144472B2
公开(公告)日：2021-10-12
申请号：US16367103
申请日：2019-03-27
Applicant: Intel Corporation
Inventor： Scott Dion Rodgers , Robert S. Chappell , Barry E. Huntley
IPC: G06F12/1009 , G06F12/1027 , G06F12/14
Abstract: An apparatus and method for managing different page tables for different privilege levels. For example, one embodiment of a processor comprises: a first control register to store a first base address associated with program code executed at a first privilege level; a second control register to store a second base address associated with program code executed at a second privilege level lower than the first privilege level; and address translation circuitry to identify a first base translation table using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level.
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15.发明授权公开(公告)号：US10452403B2
公开(公告)日：2019-10-22
申请号：US14866875
申请日：2015-09-26
Applicant: Intel Corporation
Inventor： Hong Wang , John P. Shen , Edward T. Grochowski , Richard A. Hankins , Gautham N. Chinya , Bryant E. Bigbee , Shivnandan D. Kaushik , Xiang Chris Zou , Per Hammarlund , Scott Dion Rodgers , Xinmin Tian , Anil Aggawal , Prashant Sethi , Baiju V. Patel , James P Held
Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
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Patent Agency Ranking
公开(公告)号：US10180911B2
公开(公告)日：2019-01-15
申请号：US15620663
申请日：2017-06-12
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
IPC: G06F12/00 , G06F12/1027 , G06F12/0875 , G06F12/1045 , G06F9/455 , G06F12/02 , G06F12/1036 , G06F12/1009
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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公开(公告)号：US09535838B2
公开(公告)日：2017-01-03
申请号：US13691106
申请日：2012-11-30
Applicant: Intel Corporation
Inventor： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
CPC classification number: G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。
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公开(公告)号：US09372807B2
公开(公告)日：2016-06-21
申请号：US14867027
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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公开(公告)号：US09372806B2
公开(公告)日：2016-06-21
申请号：US14867024
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard A Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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公开(公告)号：US09330021B2
公开(公告)日：2016-05-03
申请号：US14867020
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard A Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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