公开(公告)号：US20230245974A1

公开(公告)日：2023-08-03

申请号：US18131829

申请日：2023-04-06

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark BOHR ,  Rajabali KODURI ,  Leonard NEIBERG ,  Altug KOKER ,  Swaminathan SIVAKUMAR

IPC: H01L23/538 ,  H01L21/78 ,  H01L21/66 ,  H01L23/528 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5386 ,  H01L21/78 ,  H01L22/20 ,  H01L23/528 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L24/94 ,  H01L25/18 ,  H01L23/481

Abstract: A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure.

公开(公告)号：US20230005921A1

公开(公告)日：2023-01-05

申请号：US17943038

申请日：2022-09-12

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  Abhishek SHARMA ,  Wilfred GOMES ,  Pushkar RANADE ,  Kuljit S. BAINS ,  Tahir GHANI ,  Anand MURTHY

IPC: H01L27/108 ,  G11C5/06

Abstract: A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power.

公开(公告)号：US20220308995A1

公开(公告)日：2022-09-29

申请号：US17214835

申请日：2021-03-27

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Adrian C. MOGA ,  Abhishek SHARMA

IPC: G06F12/0802

Abstract: Three-dimensional (3D) DRAM integrated in the same package as compute logic enable forming high-density caches. In one example, an integrated 3D DRAM includes a large on-de cache (such as a level 4 (L4) cache), a large on-die memory-side cache, or both an L4 cache and a memory-side cache. One or more tag caches cache recently accessed tags from the L4 cache, the memory-side cache, or both. A cache controller in the compute logic is to receive a request from one of the processor cores to access an address and compare tags in the tag cache with the address. In response to a hit in the tag cache, the cache controller accesses data from the cache at a location indicated by an entry in the tag cache, without performing a tag lookup in the cache.

公开(公告)号：US20220302051A1

公开(公告)日：2022-09-22

申请号：US17836117

申请日：2022-06-09

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark BOHR ,  Doug INGERLY ,  Rajesh KUMAR ,  Harish KRISHNAMURTHY ,  Nachiket Venkappayya DESAI

IPC: H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.

公开(公告)号：US20210225808A1

公开(公告)日：2021-07-22

申请号：US17226967

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Wilfred GOMES ,  Rajesh KUMAR ,  Pooya TADAYON ,  Doug INGERLY

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US20240224504A1

公开(公告)日：2024-07-04

申请号：US18089957

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Pushkar RANADE ,  Wilfred GOMES ,  Sagar SUTHRAM ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H10B12/00

CPC classification number: H01L27/1082 ,  H01L27/10873 ,  H01L29/1608

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that include DRAM using wide band gap materials, such as SiC or GaN to reduce transistor leakage. In addition, transistors may be fabricated adding one or more extra layers between a source and a drain of a transistor and the contact of the source of the drain to increase the effective electrical gate length of the transistor to further reduce leakage. In addition, for these transistors, a thickness of the body below the gate may be made narrow to improve gate control. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222469A1

公开(公告)日：2024-07-04

申请号：US18089966

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66893

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use high voltage transistors within a SiC layer that are coupled with one or more transistors in one or more other layers in a cascode format in order to switch the high voltage transistors in the SiC layer using low voltages. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222272A1

公开(公告)日：2024-07-04

申请号：US18090838

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Christopher M. PELTO ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L25/105

Abstract: Stitched dies having double interconnects are described. For example, an integrated circuit structure includes a first die including a first device layer, a first plurality of metallization layers over the first device layer, and a first conductive interconnection over the first plurality of metallization layers. The integrated circuit structure also includes a second die separated from the first die by a scribe region, the second die including a second device layer, a second plurality of metallization layers over the second device layer, and a second conductive interconnection over the second plurality of metallization layers. The second conductive interconnection extends over the scribe region and is coupled to the first conductive interconnection.

公开(公告)号：US20240222228A1

公开(公告)日：2024-07-04

申请号：US18089931

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Wilfred GOMES ,  Anand S. MURTHY ,  Tahir GHANI ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L23/48 ,  H01L21/02 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L25/065 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/0262 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/13 ,  H01L25/0657 ,  H01L27/088 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2924/05032 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for semiconductor packages that use devices within an SiC layer coupled with devices within a GaN layer proximate to the SiC to convert a high voltage source to the package, e.g. greater than 1 kV, to 1-1.8 V used by components within the package. The devices may be transistors. The voltage conversion will allow increased power to be supplied to the package. Other embodiments may be described and/or claimed.

公开(公告)号：US20240113025A1

公开(公告)日：2024-04-04

申请号：US17958283

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Pushkar RANADE ,  Sagar SUTHRAM ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53209 ,  H01L23/5283 ,  H01L29/0673

Abstract: Embodiments disclosed herein include an integrated circuit structure. In an embodiment, the integrated circuit structure comprises an interlayer dielectric (ILD), and an opening in the ILD. In an embodiment, a first layer lines the opening, and a second layer lines the first layer. In an embodiment, the second layer comprises a semi-metal or transition metal dichalcogenide (TMD). The integrated circuit structure may further comprise a third layer over the second layer.