公开(公告)号：US20150380309A1

公开(公告)日：2015-12-31

申请号：US14315718

申请日：2014-06-26

Applicant: Intermolecular Inc. ,  GLOBALFOUNDRIES, Inc.

Inventor： Salil Mujumdar ,  Amol Joshi ,  Kevin Kashefi ,  Albert Sanghyup Lee ,  Abhijit Pethe ,  Bin Yang

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L29/517 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/02312 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/285 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal-insulator-semiconductor (MIS) contacts for germanium and its alloys include insulator layers of oxygen-deficient metal oxide deposited by atomic layer deposition (ALD). The oxygen deficiency reduces the tunnel barrier resistance of the insulator layer while maintaining the layer's ability to prevent Fermi-level pinning at the metal/semiconductor interface. The oxygen deficiency is controlled by optimizing one or more ALD parameters such as shortened oxidant pulses, use of less-reactive oxidants such as water, heating the substrate during deposition, TMA “cleaning” of native oxide before deposition, and annealing after deposition. Secondary factors include reduced process-chamber pressure, cooled oxidant, and shortened pulses of the metal precursor.

Abstract translation: 用于锗及其合金的金属 - 绝缘体 - 半导体（MIS）触点包括通过原子层沉积（ALD）沉积的缺氧金属氧化物的绝缘体层。 缺氧会降低绝缘体层的隧道势垒阻力，同时保持层在金属/半导体界面处防止费米能级钉扎的能力。 通过优化一个或多个ALD参数，例如缩短的氧化剂脉冲，使用较少反应性的氧化剂例如水，在沉积期间加热衬底，在沉积之前对自然氧化物进行TMA“清洁”，以及沉积后的退火来优化一个或多个ALD参数来控制氧缺乏。 次要因素包括降低的处理室压力，冷却的氧化剂和金属前体的缩短的脉冲。

公开(公告)号：US20150140834A1

公开(公告)日：2015-05-21

申请号：US14083124

申请日：2013-11-18

Applicant: Intermolecular Inc.

Inventor： Kevin Kashefi ,  Frank Greer

IPC: H01L21/02 ,  H01L29/51

CPC classification number: H01L21/02304 ,  H01L21/02046 ,  H01L21/02181 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/28194 ,  H01L29/517

Abstract: Methods and apparatus for processing using a plasma source for the treatment of semiconductor surfaces are disclosed. The apparatus includes an outer vacuum chamber enclosing a substrate support, a plasma source (either a direct plasma or a remote plasma), and an optional showerhead. Other gas distribution and gas dispersal hardware may also be used. The plasma source may be used to generate activated species operable to alter the surface of the semiconductor materials. Further, the plasma source may be used to generate activated species operable to enhance the nucleation of deposition precursors on the semiconductor surface.

Abstract translation: 公开了使用等离子体源处理半导体表面的方法和装置。 该装置包括封闭衬底支撑件的外部真空室，等离子体源（直接等离子体或远程等离子体）和可选的喷头。 也可以使用其他气体分配和气体分散硬件。 等离子体源可用于产生可操作以改变半导体材料的表面的活化物质。 此外，等离子体源可以用于产生可操作以增强半导体表面上的沉积前体的成核的活化物质。

公开(公告)号：US20140262749A1

公开(公告)日：2014-09-18

申请号：US13804265

申请日：2013-03-14

Applicant: Intermolecular, Inc.

Inventor： Ashish Bodke ,  Olov Karlsson ,  Kevin Kashefi ,  Chi-I Lang ,  Dipankar Pramanik ,  Hong Sheng Yang ,  Xuena Zhang

IPC: C23C14/35

CPC classification number: B01J19/0046 ,  B01J2219/0043 ,  B01J2219/00443 ,  B01J2219/00527 ,  B01J2219/00635 ,  B01J2219/0075 ,  B01J2219/00756 ,  C23C14/042 ,  C23C14/345

Abstract: Combinatorial processing of a substrate comprising site-isolated sputter deposition and site-isolated plasma processing can be performed in a same process chamber. The process chamber, configured to perform sputter deposition and plasma processing, comprises a grounded shield having at least an aperture disposed above the substrate to form a small, dark space gap to reduce or eliminate any plasma formation within the gap. The plasma processing may include plasma etching or plasma surface treatment.

Abstract translation: 包含现场分离的溅射沉积和位置分离等离子体处理的基板的组合处理可以在相同的处理室中进行。 被配置为执行溅射沉积和等离子体处理的处理室包括接地屏蔽，其具有设置在衬底上方的至少一个孔，以形成小的，较暗的空间间隙，以减少或消除间隙内的任何等离子体形成。 等离子体处理可以包括等离子体蚀刻或等离子体表面处理。

公开(公告)号：US09368721B1

公开(公告)日：2016-06-14

申请号：US14553443

申请日：2014-11-25

Applicant: Intermolecular, Inc.

Inventor： Ashish Bodke ,  Mark Clark ,  Kevin Kashefi ,  Prashant B. Phatak

IPC: H01L45/00

CPC classification number: H01L45/1286 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/149

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). A structure including diamond-like carbon (DLC) can be used to surround the semiconductor layer of the MSM stack. The high thermal conductivity of the DLC structure may serve to remove heat from the selector device while higher currents are flowing through the selector element. This may lead to improved reliability and improved endurance.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少未选择器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于多层膜堆叠（例如金属 - 半导体 - 金属（MSM）堆叠）。 可以使用包括类金刚石碳（DLC）的结构来围绕MSM堆叠的半导体层。 DLC结构的高热导率可用于在较高的电流流过选择器元件时从选择器装置移除热量。 这可能导致改进的可靠性和耐久性。

公开(公告)号：US09337238B1

公开(公告)日：2016-05-10

申请号：US14524801

申请日：2014-10-27

Applicant: Intermolecular, Inc.

Inventor： Kevin Kashefi ,  Ashish Bodke ,  Mark Clark ,  Prashant B. Phatak ,  Dipankar Pramanik

IPC: H01L27/24 ,  H01L33/50 ,  H01L33/32 ,  H01L33/30 ,  H01L33/28 ,  H01L33/40

CPC classification number: H01L27/2409 ,  H01L27/15 ,  H01L33/285 ,  H01L33/30 ,  H01L33/32 ,  H01L33/40 ,  H01L33/502 ,  H01L45/08

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a photo-luminescent or electro-luminescent material. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or combinations thereof.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于多层膜堆叠（例如金属 - 半导体 - 金属（MSM）堆叠）。 选择元件的半导体层可以包括光致发光或电致发光材料。 MSM的导电材料可以包括钨，氮化钛，碳或其组合。

公开(公告)号：US20160118440A1

公开(公告)日：2016-04-28

申请号：US14524801

申请日：2014-10-27

Applicant: Intermolecular, Inc.

Inventor： Kevin Kashefi ,  Ashish Bodke ,  Mark Clark ,  Prashant B. Phatak ,  Dipankar Pramanik

IPC: H01L27/24 ,  H01L33/40 ,  H01L33/32 ,  H01L33/50 ,  H01L33/28 ,  H01L33/30

CPC classification number: H01L27/2409 ,  H01L27/15 ,  H01L33/285 ,  H01L33/30 ,  H01L33/32 ,  H01L33/40 ,  H01L33/502 ,  H01L45/08

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a photo-luminescent or electro-luminescent material. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or combinations thereof.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于多层膜堆叠（例如金属 - 半导体 - 金属（MSM）堆叠）。 选择元件的半导体层可以包括光致发光或电致发光材料。 MSM的导电材料可以包括钨，氮化钛，碳或其组合。

公开(公告)号：US20150303057A1

公开(公告)日：2015-10-22

申请号：US14253906

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES, Inc. ,  Intermolecular, Inc.

Inventor： Bongki Lee ,  Paul Besser ,  Kevin Kashefi ,  Olov Karlsson ,  Ashish Bodke ,  Ratsamee Limdulpaiboon ,  Divya Pisharoty ,  Nobi Fuchigami

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L21/02181 ,  H01L21/02164 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括在FET区域中形成电介质氧化物材料的中间层并覆盖在半导体衬底上。 沉积在中间层上方的高K电介质层。 氟被并入到中间层和/或高K电介质层中。

公开(公告)号：US20150140838A1

公开(公告)日：2015-05-21

申请号：US14083761

申请日：2013-11-19

Applicant: Intermolecular Inc.

Inventor： Kevin Kashefi ,  Amol Joshi ,  Salil Mujumdar

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/517 ,  C23C16/405 ,  C23C16/45527 ,  C23C16/56 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02318 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6659

Abstract: Methods and apparatus for forming a dielectric layer for use as a gate dielectric are provided. A high-k layer is formed with first ALD process using a halogen-based precursor. The metal in the halogen-based precursor may be at least one of hafnium, zirconium, or titanium. The halogen in the halogen-based precursor may be at least one of fluorine, chlorine, or iodine. In some embodiments, the halogen-based metal precursor includes hafnium chloride. The remainder of the high-k layer is formed with second ALD process using a metal organic-based precursor. The metal in the metal organic-based precursor may be at least one of hafnium, zirconium, or titanium. The organic ligands in the metal organic-based precursor may be at least one of β-diketonate precursors, alkoxide precursors, amino precursors. In some embodiments, the metal organic-based precursor includes amino precursors.

Abstract translation: 提供了形成用作栅极电介质的电介质层的方法和装置。 使用卤素前体的第一ALD工艺形成高k层。 卤素前体中的金属可以是铪，锆或钛中的至少一种。 卤素前体中的卤素可以是氟，氯或碘中的至少一种。 在一些实施方案中，卤素基金属前体包括氯化铪。 高k层的其余部分由使用金属有机基前体的第二ALD工艺形成。 金属有机基前体中的金属可以是铪，锆或钛中的至少一种。 金属有机基前体中的有机配体可以是β-二酮前体，醇盐前体，氨基前体中的至少一种。 在一些实施方案中，金属有机基前体包括氨基前体。

公开(公告)号：US20150064361A1

公开(公告)日：2015-03-05

申请号：US14018112

申请日：2013-09-04

Applicant: Intermolecular Inc.

Inventor： Frank Greer ,  Amol Joshi ,  Kevin Kashefi

IPC: B05D3/06

CPC classification number: C23C16/45536 ,  C23C16/45527

Abstract: Irradiation with ultraviolet (UV) light during atomic layer deposition (ALD) can be used to cleave unwanted bonds on the layer being formed (e.g., trapped precursor ligands or process-gas molecules). Alternatively, the UV irradiation can be used to excite the targeted bonds so they may be more easily cleaved by other means. The use of UV may enable the formation of low-defect-density films at lower deposition temperatures (e.g.,

Abstract translation: 可以使用在原子层沉积（ALD）期间用紫外线（UV）光照射在所形成的层（例如，捕获的前体配体或工艺气体分子）上切割不需要的键。 或者，可以使用UV照射来激发目标键，使得它们可以通过其它方式更容易地被切割。 使用UV可以在较低的沉积温度（例如<250℃）下形成低缺陷密度的膜，或者减少对高温后沉积退火的需要，从而提高在热处理后形成的器件的质量， 敏感材料如锗。