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公开(公告)号：US09040407B2
公开(公告)日：2015-05-26
申请号：US14043079
申请日：2013-10-01
IPC分类号： H05K3/42 , H01L23/48 , H01L23/532 , H01L21/768
CPC分类号： H05K3/423 , H01L21/76844 , H01L21/76846 , H01L21/76858 , H01L21/76898 , H01L23/481 , H01L23/53209 , H01L23/53214 , H01L23/53238 , H01L23/53242 , H01L23/53257 , H01L2924/0002 , Y10T428/12764 , H01L2924/00
摘要： A method including depositing an alloying layer along a sidewall of an opening and in direct contact with a seed layer, the alloying layer includes a crystalline structure that cannot serve as a seed for plating a conductive material, exposing the opening to an electroplating solution including the conductive material, the conductive material is not present in the alloying layer, applying an electrical potential to a cathode causing the conductive material to deposit from the electroplating solution onto the cathode exposed at the bottom of the opening and causing the opening to fill with the conductive material, the cathode includes an exposed portion of the seed layer and excludes the alloying layer, and forming a first intermetallic compound along an intersection between the alloying layer and the conductive material, the first intermetallic compound is formed as a precipitate within a solid solution of the alloying layer and the conductive material.
摘要翻译： 一种方法，包括沿着开口的侧壁沉积合金层并与种子层直接接触，所述合金化层包括不能用作电镀导电材料的种子的晶体结构，将开口暴露于包括 导电材料不存在于合金化层中，向阴极施加电势，导致导电材料从电镀溶液沉积到露出在开口底部的阴极上并使开口填充导电材料 材料中，阴极包括种子层的暴露部分，不包括合金层，沿着合金层和导电材料之间的交点形成第一金属间化合物，第一金属间化合物形成为沉淀在固溶体 合金层和导电材料。
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公开(公告)号：US20150056804A1
公开(公告)日：2015-02-26
申请号：US14522633
申请日：2014-10-24
IPC分类号： H01L21/768 , H01L21/683 , H01L23/00
CPC分类号： H01L21/76898 , H01L21/6835 , H01L21/6836 , H01L21/76879 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2221/68359 , H01L2224/03462 , H01L2224/03622 , H01L2224/0401 , H01L2224/05556 , H01L2224/05572 , H01L2224/05611 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2224/11 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/94 , Y10T29/41 , H01L2924/00012 , H01L2924/00014 , H01L2224/03 , H01L2924/014
摘要： According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad.
摘要翻译： 根据本发明的一个实施例，提供了一种在衬底中电镀TSV孔的方法。 TSV孔可以包括终止于导电焊盘的开口端，布线层的堆叠以及多个芯片互连。 电镀TSV的方法可以包括将处理器附接到多个芯片互连件，处理器具有与多个芯片互连电接触的导电层; 将包括导电垫的TSV孔的封闭端暴露于电解质溶液中; 以及沿着从所述导电层到所述导电焊盘的电路径施加电势，从而导致来自所述电解质溶液的导电材料沉积在所述导电焊盘和所述TSV孔内，所述电路包括所述导电层，所述多个芯片互连， 布线层叠和导电垫。
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公开(公告)号：US08927427B2
公开(公告)日：2015-01-06
申请号：US13872371
申请日：2013-04-29
IPC分类号： H01L21/44 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L2924/0002 , H01L2924/00
摘要： A method including introducing a dopant into a region of a substrate, etching a deep trench in the substrate through the region, gettering impurities introduced during etching of the deep trench using a pentavalent ion formed from a reaction between an element of the substrate and the dopant, wherein the charge of the pentavalent ion attracts the impurities, and filling the deep trench with a conductive material.
摘要翻译： 一种方法，包括将掺杂剂引入到衬底的区域中，通过该区域蚀刻衬底中的深沟槽，利用由衬底的元素和掺杂剂之间的反应形成的五价离子来吸收在蚀刻深沟槽期间引入的杂质 其中五价离子的电荷吸引杂质，并用导电材料填充深沟槽。
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14.发明申请ELECTRICAL LEAKAGE REDUCTION IN STACKED INTEGRATED CIRCUITS HAVING THROUGH-SILICON-VIA (TSV) STRUCTURES 有权具有穿透硅（TSV）结构的堆叠集成电路中的电气泄漏减少公开(公告)号：US20150004749A1
公开(公告)日：2015-01-01
申请号：US14487439
申请日：2014-09-16
发明人： Christopher N. Collins , Mukta G. Farooq , Troy L. Graves-Abe , Joyce C. Liu , Gerd Pfeiffer , Thuy L. Tran-Quinn
IPC分类号： H01L25/065
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/5384 , H01L29/32 , H01L2224/16225 , H01L2225/06541 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers).
摘要翻译： 已经证明用于3D应用的TSV（通过衬底通孔）的形成缺陷取决于所采用的起始半导体衬底的类型。 除了通过博世处理初始形成TSV之外，背面3D晶片处理也显示了对衬底类型的缺陷依赖性。 通过利用以1e4 / cc（每立方厘米颗粒）和1e7 / cc之间的密度并且具有小于55nm（纳米）的等效直径的体积微观缺陷（BMD）来实现高产率的TSV形成。
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公开(公告)号：US20140027296A1
公开(公告)日：2014-01-30
申请号：US14043079
申请日：2013-10-01
IPC分类号： H05K3/42
CPC分类号： H05K3/423 , H01L21/76844 , H01L21/76846 , H01L21/76858 , H01L21/76898 , H01L23/481 , H01L23/53209 , H01L23/53214 , H01L23/53238 , H01L23/53242 , H01L23/53257 , H01L2924/0002 , Y10T428/12764 , H01L2924/00
摘要： A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material. The structure including a first intermetallic compound separating the diffusion barrier from the conductive material, the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, the alloying material is at least one of the materials selected from the group of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; and a first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the diffusion barrier and the first intermetallic compound.
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16.发明授权Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures 有权具有通硅通孔（TSV）结构的堆叠集成电路中的漏电减少公开(公告)号：US08907494B2
公开(公告)日：2014-12-09
申请号：US13826628
申请日：2013-03-14
发明人： Christopher N. Collins , Mukta G. Farooq , Troy L. Graves-Abe , Joyce C. Liu , Gerd Pfeiffer , Thuy L. Tran-Quinn
IPC分类号： H01L23/52 , H01L23/538 , H01L29/32
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/5384 , H01L29/32 , H01L2224/16225 , H01L2225/06541 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers).
摘要翻译： 已经证明用于3D应用的TSV（通过衬底通孔）的形成缺陷取决于所采用的起始半导体衬底的类型。 除了通过博世处理初始形成TSV之外，背面3D晶片处理也显示了对衬底类型的缺陷依赖性。 可以通过利用以1e4 / cc（每立方厘米颗粒）和1e7 / cc之间的密度并且具有小于55nm（纳米）的当量直径的体积微观缺陷（BMD）来实现高产率的TSV形成。
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17.发明申请METHOD OF FORMING A THROUGH-SILICON VIA UTILIZING A METAL CONTACT PAD IN A BACK-END-OF-LINE WIRING LEVEL TO FILL THE THROUGH-SILICON VIA 有权通过利用金属接触垫在后端线接线层中形成穿透硅的方法来填充穿透硅公开(公告)号：US20140342552A1
公开(公告)日：2014-11-20
申请号：US14446634
申请日：2014-07-30
IPC分类号： H01L21/768 , H01L23/00 , H01L21/306
CPC分类号： H01L21/76898 , H01L21/2885 , H01L21/306 , H01L21/6835 , H01L21/76841 , H01L21/76846 , H01L21/76879 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2221/1084 , H01L2221/68372 , H01L2221/68381 , H01L2224/0401 , H01L2224/05022 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/13023 , H01L2224/131 , H01L2924/00014 , H01L2924/07802 , H01L2924/00012 , H01L2924/01074 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： A method for fabricating through-silicon vias (TSVs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill TSVs with plated-conductive material (e.g., copper) from an electroplating solution. Moreover, the method provides a way to fill high aspect ratio TSVs with minimal additional semiconductor fabrication process steps, which can increase the silicon area that is available for forming additional electronic components on integrated circuits.
摘要翻译： 提供了一种用于制造用于半导体器件的硅通孔（TSV）的方法。 具体地，该方法包括在后端线路布线层中利用铜接触焊盘，其中铜接触焊盘用作执行电镀技术的阴极，用电镀导电材料（例如铜）填充TSV 解。 此外，该方法提供了通过最小的附加半导体制造工艺步骤填充高纵横比TSV的方法，其可以增加可用于在集成电路上形成附加电子部件的硅面积。
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公开(公告)号：US20140227870A1
公开(公告)日：2014-08-14
申请号：US14255067
申请日：2014-04-17
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L21/2885 , H01L21/306 , H01L21/6835 , H01L21/76841 , H01L21/76846 , H01L21/76879 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2221/1084 , H01L2221/68372 , H01L2221/68381 , H01L2224/0401 , H01L2224/05022 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/13023 , H01L2224/131 , H01L2924/00014 , H01L2924/07802 , H01L2924/00012 , H01L2924/01074 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： A method for fabricating through-silicon vias (TSVs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill TSVs with plated-conductive material (e.g., copper) from an electroplating solution. Moreover, the method provides a way to fill high aspect ratio TSVs with minimal additional semiconductor fabrication process steps, which can increase the silicon area that is available for forming additional electronic components on integrated circuits.
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公开(公告)号：US20140027912A1
公开(公告)日：2014-01-30
申请号：US14043127
申请日：2013-10-01
IPC分类号： H01L23/532
CPC分类号： H05K3/423 , H01L21/76844 , H01L21/76846 , H01L21/76858 , H01L21/76898 , H01L23/481 , H01L23/53209 , H01L23/53214 , H01L23/53238 , H01L23/53242 , H01L23/53257 , H01L2924/0002 , Y10T428/12764 , H01L2924/00
摘要： A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material. The structure including a first intermetallic compound separating the diffusion barrier from the conductive material, the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, the alloying material is at least one of the materials selected from the group of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; and a first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the diffusion barrier and the first intermetallic compound.
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公开(公告)号：US20140027911A1
公开(公告)日：2014-01-30
申请号：US14043104
申请日：2013-10-01
IPC分类号： H01L23/532
CPC分类号： H05K3/423 , H01L21/76844 , H01L21/76846 , H01L21/76858 , H01L21/76898 , H01L23/481 , H01L23/53209 , H01L23/53214 , H01L23/53238 , H01L23/53242 , H01L23/53257 , H01L2924/0002 , Y10T428/12764 , H01L2924/00
摘要： A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material. The structure including a first intermetallic compound separating the diffusion barrier from the conductive material, the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, the alloying material is at least one of the materials selected from the group of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; and a first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the diffusion barrier and the first intermetallic compound.
摘要翻译： 一种形成在开口中的结构，其具有由非金属材料限定的基本上垂直的侧壁，并且具有由导电垫限定的基本上水平的底部，该结构包括覆盖侧壁的扩散阻挡层和由导电材料构成的填充物。 所述结构包括将所述扩散阻挡物与所述导电材料分离的第一金属间化合物，所述第一金属间化合物包括合金材料和所述导电材料，并且机械地结合到所述导电材料上，所述合金材料是选自以下的至少一种材料： 铬，锡，镍，镁，钴，铝，锰，钛，锆，铟，钯和银的组合; 以及位于所述扩散阻挡层和所述第一金属间化合物之间且平行于所述开口的侧壁的第一高摩擦界面，其中所述第一高摩擦界面导致所述扩散阻挡层和所述第一金属间化合物之间的机械结合。
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