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    DESIGN STRUCTURE FOR MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT
    11.
    发明申请
    DESIGN STRUCTURE FOR MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT 失效
    在集成电路中测量功耗的设计结构

    公开(公告)号：US20090153324A1

    公开(公告)日：2009-06-18

    申请号：US12046501

    申请日：2008-03-12

    申请人： Kenneth Joseph Goodnow ,  Clarence Rosser Ogilvie ,  Nitin Sharma ,  Sebastian Theodore Ventrone ,  Charles S. Woodruff

    发明人： Kenneth Joseph Goodnow ,  Clarence Rosser Ogilvie ,  Nitin Sharma ,  Sebastian Theodore Ventrone ,  Charles S. Woodruff

    IPC分类号： G08B21/00

    CPC分类号： G01R31/31721

    摘要： An design structure for measuring power consumed during operation of an integrated circuit. The design structure including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal.

    摘要翻译： 一种用于测量集成电路运行期间消耗的功率的设计结构。 该设计结构包括：具有输入和输出的数据处理电路，所述数据处理电路被配置为基于输入数据信号产生输出数据信号; 功率测量电路，被配置为测量由所述输入信号产生所述输出信号时由所述处理电路消耗的电力量;连接在所述处理电路和所述处理电路的电源之间的所述功率测量电路; 以及存储元件，被配置为存储包含表示由处理电路消耗的电力量的值的标签，用于从输入数据信号生成输出数据信号，以及（a）输入数据信号的输入数据或（b ）指向输入数据信号的输入数据的指针。

    True/complement output bus for reduced simulataneous switching noise
    12.
    发明授权
    True/complement output bus for reduced simulataneous switching noise 失效
    用于减少模拟开关噪声的真/补输出总线

    公开(公告)号：US5874833A

    公开(公告)日：1999-02-23

    申请号：US794041

    申请日：1997-02-03

    申请人： Patrick Edward Perry ,  Sebastian Theodore Ventrone

    发明人： Patrick Edward Perry ,  Sebastian Theodore Ventrone

    IPC分类号： H03K19/003 ,  H03K19/0175

    CPC分类号： H03K19/00346

    摘要： A true/complement integrated circuit device is disclosed for reducing an amount of simultaneous switching on a bus between a current state and a next state. The device includes a current state register connected to the bus for outputting the current state onto the bus during a first clock cycle. A next state register is provided for containing the next state, wherein the next state is a pending state of the bus intended for a next clock cycle. A comparison circuit compares a current state value in the current state register with a next state value in the next state register on a bit-by-bit basis to determine if the current state value and the next state value are of a same polarity or of an opposite polarity. A circuit is provided for determining a ratio of switching signals from an output of the bit-by-bit comparisons by the comparison circuit. The ratio determining circuit further generates a true/complement (T/C) signal having a first state if it is determined that more than a prescribed percentage of bits are in transition, the T/C signal having a second state otherwise. Lastly, a circuit is provided for complementing the bits of the next state register in response to the T/C signal being in the first state, and not complementing the bits of the next state register in response to the T/C signal being in the second state, prior to being transferred into the current state register and output onto the bus during the next clock cycle.

    摘要翻译： 公开了一种真/补体集成电路装置，用于减少在当前状态和下一状态之间的总线上的同时开关量。 该装置包括连接到总线的当前状态寄存器，用于在第一时钟周期期间将当前状态输出到总线上。 提供下一个状态寄存器用于包含下一个状态，其中下一个状态是下一个时钟周期的总线的待处理状态。 比较电路将当前状态寄存器中的当前状态值与下一状态寄存器中的下一状态值逐位进行比较，以确定当前状态值和下一状态值是否具有相同的极性，或者 相反的极性。 提供了一种电路，用于确定比较电路中逐位比较输出的开关信号的比例。 比例确定电路进一步产生具有第一状态的真/补（T / C）信号，如果确定多于一定比例的位正在转换，否则T / C信号具有第二状态。 最后，提供一个电路来补偿下一个状态寄存器的位，以响应于T / C信号处于第一状态，并且不响应于T / C信号位于下一个状态寄存器的位 第二状态，在被转移到当前状态寄存器之前，并且在下一个时钟周期内输出到总线上。

    Concurrent multitasking in a uniprocessor
    13.
    发明授权
    Concurrent multitasking in a uniprocessor 失效
    在单处理器中并发多任务

    公开(公告)号：US5867725A

    公开(公告)日：1999-02-02

    申请号：US618689

    申请日：1996-03-21

    申请人： Patrick Wai-Wah Fung ,  Sebastian Theodore Ventrone

    发明人： Patrick Wai-Wah Fung ,  Sebastian Theodore Ventrone

    IPC分类号： G06F9/38 ,  G06F9/46

    CPC分类号： G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/462

    摘要： A superscalar uniprocessor that performs concurrent multi-task processing is provided. The processor of the present invention maintains a complete set of program address, memory control and general data registers for each task executing concurrently within the microprocessor, allowing independent control of the program flows. Each set of registers are associated with only one task and are utilized by the memory control and execution units to execute the associated task. The processor includes an instruction fetcher and memory management unit that retrieves an instruction from memory for a given task, as directed by the task's address and control registers, and attaches a task tag to the retrieved instruction that identifies that task. The superscalar processor has a plurality of execution units that can execute a plurality of tasks simultaneously, and a dispatch unit that sends a retrieved instruction and its attached task tag to one of the plurality of execution units for execution. The instruction's task tag identifying the task is then associated with any result data that results from the execution of the instruction. The addition of task tag information in the program flow and in the register file provides for process utilization of execution resources simultaneously with, and substantially independently from other processes, thereby substantially enhancing concurrent multitasking in the superscalar uniprocessor.

    摘要翻译： 提供了执行并发多任务处理的超标量单处理器。 本发明的处理器为在微处理器内同时执行的每个任务维护一整套程序地址，存储器控制和通用数据寄存器，从而允许对程序流的独立控制。 每组寄存器仅与一个任务相关联，并被存储器控制和执行单元用于执行相关联的任务。 处理器包括指令读取器和存储器管理单元，其根据任务地址和控制寄存器的指示从给定任务的存储器检索指令，并且将任务标签附加到识别该任务的检索指令中。 超标量处理器具有可以同时执行多个任务的多个执行单元，以及发送单元，其将检索到的指令及其附加的任务标签发送到多个执行单元之一用于执行。 然后，将指令的任务标签识别任务与与指令执行产生的任何结果数据相关联。 在程序流程和寄存器文件中添加任务标签信息提供了与其他进程同时进行并且基本独立于其他进程的执行资源的进程利用，从而大大增强了超标量单处理器中的并发多任务处理。

    Self regulating temperature/performance/voltage scheme for micros (X86)
    17.
    发明授权
    Self regulating temperature/performance/voltage scheme for micros (X86) 有权
    微调自适应温度/性能/电压方案（X86）

    公开(公告)号：US6119241A

    公开(公告)日：2000-09-12

    申请号：US183342

    申请日：1998-10-30

    申请人： Michel Salib Michail ,  Wilbur David Pricer ,  Sebastian Theodore Ventrone

    发明人： Michel Salib Michail ,  Wilbur David Pricer ,  Sebastian Theodore Ventrone

    IPC分类号： G06F1/08 ,  G06F1/20 ,  G06F1/32 ,  G06F1/26

    CPC分类号： G06F1/324 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3296 ,  Y02B60/1217 ,  Y02B60/1285

    摘要： A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.

    摘要翻译： 一种处理器，通过使用包括电压，时钟和由处理器或其系统执行的操作的变量的层次来机会地优化性能。 本发明通过定义各种状态来实现性能优化，目的在于处理器执行单元正在运行时处理器处于加速电压和时钟的最佳性能状态。 状态由逻辑网络基于由温度传感器和性能控制提供的信息来选择。 逻辑网络可以设想为一个UP-DOWN计数器。 根据条件，计数器可以向上或向下进入状态“梯子”。

    Anticipating cache memory loader and method
    18.
    发明授权
    Anticipating cache memory loader and method 失效
    预测缓存内存加载器和方法

    公开(公告)号：US6026471A

    公开(公告)日：2000-02-15

    申请号：US751468

    申请日：1996-11-19

    申请人： Kenneth Joseph Goodnow ,  Clarence Rosser Ogilvie ,  Wilbur David Pricer ,  Sebastian Theodore Ventrone

    发明人： Kenneth Joseph Goodnow ,  Clarence Rosser Ogilvie ,  Wilbur David Pricer ,  Sebastian Theodore Ventrone

    IPC分类号： G06F9/46 ,  G06F12/08 ,  G06F12/10 ,  G06F17/12

    CPC分类号： G06F12/0862 ,  G06F9/461 ,  G06F2212/6024

    摘要： According to the present invention, an anticipating cache memory loader is provided to "pre-load" the cache with the data and instructions most likely to be needed by the CPU once the currently executing task is completed or interrupted. The data and instructions most likely to be needed after the currently executing task is completed or executed is the same data and instructions that were loaded into the cache at the time the next scheduled task was last preempted or interrupted. By creating and storing an index to the contents of the cache for various tasks at the point in time the tasks are interrupted, the data and instructions previously swapped out of the cache can be retrieved from main memory and restored to the cache when needed. By using available bandwidth to pre-load the cache for the next scheduled task, the CPU can begin processing the next scheduled task more quickly and efficiently than if the present invention were not utilized. Using the present invention, CPU stalls will be reduced because the CPU will operate more efficiently without waiting for excessive periods of time for the cache to be loaded with relevant data and instructions.

    摘要翻译： 根据本发明，提供一种预期的高速缓存存储器加载器，用于在当前执行的任务完成或中断之后，用CPU最有可能需要的数据和指令来“预加载”高速缓存。 在完成或执行当前执行任务之后最可能需要的数据和指令是在下一个计划任务最后被抢占或中断时加载到缓存中的相同数据和指令。 通过在任务中断的时间点为各种任务创建和存储索引到高速缓存的内容，可以从主存储器中检索先前从高速缓存交换的数据和指令，并在需要时将其还原到高速缓存。 通过使用可用带宽来预加载用于下一个计划任务的高速缓存，与不利用本发明相比，CPU可以更快速和有效地开始处理下一个计划的任务。 使用本发明，CPU停止将被减少，因为CPU将更有效地操作而不用等待超时间段来缓存相关数据和指令。

    Structures including circuits for noise reduction in digital systems
    19.
    发明授权
    Structures including circuits for noise reduction in digital systems 有权
    包括数字系统降噪电路的结构

    公开(公告)号：US08037337B2

    公开(公告)日：2011-10-11

    申请号：US11946096

    申请日：2007-11-28

    申请人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    发明人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    IPC分类号： G06F1/04

    CPC分类号： G06F1/06 ,  G06F1/08 ,  G06F9/3869

    摘要： A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

    摘要翻译： 包括数字系统的设计结构。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。