公开(公告)号：US20130234326A1

公开(公告)日：2013-09-12

申请号：US13604481

申请日：2012-09-05

Applicant: Chul KIM ,  Jae Jin LEE ,  Jong Chern LEE

Inventor： Chul KIM ,  Jae Jin LEE ,  Jong Chern LEE

IPC: H01L23/00 ,  H01L21/82

CPC classification number: H01L23/562 ,  H01L21/82 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor apparatus comprises of a first semiconductor chip having a through silicon via (TSV) and a second semiconductor chip also having a TSV, wherein the respective semiconductor chips are stacked vertically and are connected through a conductive connection member without the assistance of an additional bump between the conductive connection member and the second semiconductor chip.

Abstract translation: 半导体装置包括具有贯通硅通孔（TSV）的第一半导体芯片和也具有TSV的第二半导体芯片，其中各个半导体芯片垂直堆叠并通过导电连接构件连接，而无需附加凸块 在导电连接部件和第二半导体芯片之间。

公开(公告)号：US20130105851A1

公开(公告)日：2013-05-02

申请号：US13340867

申请日：2011-12-30

Applicant: Byoung Sung KIM ,  Sang Eun LIM ,  Jae Jin LEE ,  Yeoun Chul SON

Inventor： Byoung Sung KIM ,  Sang Eun LIM ,  Jae Jin LEE ,  Yeoun Chul SON

IPC: H01L33/62

CPC classification number: H01L33/486 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49107 ,  H05K1/0268 ,  H05K1/181 ,  H05K3/3426 ,  H05K2201/09427 ,  H05K2201/10106 ,  Y02P70/613 ,  H01L2924/00014

Abstract: Exemplary embodiments of the present invention provide a light emitting diode package including a light emitting diode chip, a lead frame having a chip area on which the light emitting diode chip is arranged, and a package body supporting the lead frame. The lead frame includes a first terminal group arranged at a first side of the chip area and a second terminal group arranged at a second side of the chip area. The first terminal group and the second terminal group each include a first terminal and a second terminal, and in at least one of the first terminal group and the second terminal group, the first terminal is connected to the chip area and the second terminal is separated from the chip area. The first terminal has a first width, the second terminal has a second width, and the first width is different than the second width.

Abstract translation: 本发明的示例性实施例提供一种包括发光二极管芯片的发光二极管封装，其上布置有发光二极管芯片的芯片区域的引线框架和支撑引线框架的封装体。 引线框架包括布置在芯片区域的第一侧的第一端子组和布置在芯片区域的第二侧的第二端子组。 第一端子组和第二端子组各自包括第一端子和第二端子，并且在第一端子组和第二端子组中的至少一个中，第一端子连接到芯片区域，并且第二端子被分离 从芯片区域。 第一端子具有第一宽度，第二端子具有第二宽度，并且第一宽度不同于第二宽度。

公开(公告)号：US20120182042A1

公开(公告)日：2012-07-19

申请号：US13162676

申请日：2011-06-17

Applicant: Chun Seok JEONG ,  Jae Jin LEE

Inventor： Chun Seok JEONG ,  Jae Jin LEE

IPC: H03K19/003

CPC classification number: G11C7/20 ,  G11C29/883 ,  G11C2029/4402 ,  H01L2224/16

Abstract: A semiconductor apparatus having first and second chips includes a first operation unit disposed in the first chip, and is configured to perform a predetermined arithmetic operation for an initial code according to a first repair signal and generate a first operation code; and a second operation unit disposed in the second chip, and configured to perform the predetermined arithmetic operation for the first operation code according to a second repair signal and generate a second operation code.

Abstract translation: 具有第一和第二芯片的半导体装置包括设置在第一芯片中的第一操作单元，并且被配置为根据第一修复信号对初始码执行预定的算术运算，并生成第一操作码; 以及第二操作单元，设置在所述第二芯片中，并且被配置为根据第二修复信号对所述第一操作码执行所述预定算术运算，并生成第二操作码。

公开(公告)号：US20100252872A1

公开(公告)日：2010-10-07

申请号：US12820092

申请日：2010-06-21

Applicant: Hee Bok KANG ,  Jin Hong AHN ,  Jae Jin LEE

Inventor： Hee Bok KANG ,  Jin Hong AHN ,  Jae Jin LEE

IPC: H01L27/115

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L21/84 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7841

Abstract: A nonvolatile ferroelectric memory device includes a plurality of unit cell arrays, wherein each of the plurality of unit cell arrays includes: a bottom word line; a plurality of insulating layers formed on the bottom word line, respectively; a floating channel layer comprising a plurality of channel regions located on the plurality of insulating layers and a plurality of drain and source regions which are alternately electrically connected in series to the plurality of channel regions; a plurality of ferroelectric layers formed respectively on the plurality of channel regions of the floating channel layer; and a plurality of word lines formed on the plurality of ferroelectric layers, respectively. The unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of channel regions depending on polarity states of the plurality of ferroelectric layers.

Abstract translation: 非易失性铁电存储器件包括多个单元阵列，其中多个单元阵列中的每一个包括：底部字线; 分别形成在底部字线上的多个绝缘层; 浮动沟道层，包括位于所述多个绝缘层上的多个沟道区和与所述多个沟道区交替电连接的多个漏极和源极区; 分别形成在所述浮动沟道层的所述多个沟道区上的多个铁电层; 以及分别形成在多个铁电体层上的多个字线。 根据多个铁电层的极性状态，单元阵列通过对多个沟道区域引起不同的沟道电阻来读取和写入多个数据。

公开(公告)号：US20100074542A1

公开(公告)日：2010-03-25

申请号：US12368814

申请日：2009-02-10

Applicant: Jae Jin LEE ,  Moo Kyoung CHUNG ,  Seung Hyun CHO ,  Kyung Su KIM ,  Jun Young LEE ,  Seong Mo PARK ,  Nak Woong EUM

Inventor： Jae Jin LEE ,  Moo Kyoung CHUNG ,  Seung Hyun CHO ,  Kyung Su KIM ,  Jun Young LEE ,  Seong Mo PARK ,  Nak Woong EUM

IPC: G06F7/06 ,  G06F17/30

CPC classification number: H04N19/426 ,  H04N19/44 ,  H04N19/91

Abstract: Provided are an apparatus for decoding a minimum memory access-based context adaptive variable length code (CAVLC) of the moving picture compression standard, H.264, and a table search method for decoding a context adaptive variable length code using the same. The apparatus for decoding a context adaptive variable length code may be useful to improve an overall decoding speed since the repeated memory accesses may be reduced to 2 cycles of memory accesses by reconstructing a context adaptive variable length code table of first decoding information (TrailingOnes) and second decoding information (TotalCoefficient) into 2-step tables and storing the reconstructed 2-step tables in advance and performing a table search to decode the first decoding information and the second decoding information, by using the information stored in the 2-step tables, depending on whether the remaining bits except for the number of leading zero are present in the inputted bit stream.

Abstract translation: 提供了一种用于解码运动图像压缩标准H.264的最小存储器访问上下文自适应可变长度码（CAVLC）的装置，以及用于使用其进行上下文自适应可变长度码的解码的表搜索方法。 用于对上下文自适应可变长度码进行解码的装置对于提高整体解码速度可能是有用的，因为通过重建第一解码信息（TrailingOnes）的上下文自适应可变长度码表，可以将重复的存储器访问减少到2个周期的存储器访问， 第二解码信息（TotalCoefficient）到2步表中，并且通过使用存储在2步表中的信息，预先存储重建的两步表并执行表搜索以解码第一解码信息和第二解码信息， 取决于在输入的比特流中是否存在除了前导零的数目之外的剩余比特。

公开(公告)号：US20130001548A1

公开(公告)日：2013-01-03

申请号：US13339018

申请日：2011-12-28

Applicant: Chun Seok JEONG ,  Jae Jin LEE

Inventor： Chun Seok JEONG ,  Jae Jin LEE

IPC: H01L25/07 ,  H01L23/48

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06596

Abstract: A semiconductor apparatus includes a TSV formed to be electrically connected with another chip and a TSV test unit configured to check a capacitance component of the TSV to generate a TSV abnormality signal.

Abstract translation: 半导体装置包括被形成为与另一个芯片电连接的TSV以及被配置为检查TSV的电容分量以产生TSV异常信号的TSV测试单元。

公开(公告)号：US20090184757A1

公开(公告)日：2009-07-23

申请号：US12138554

申请日：2008-06-13

Applicant: Mi Hye KIM ,  Jae Jin LEE

Inventor： Mi Hye KIM ,  Jae Jin LEE

IPC: G05F1/10

CPC classification number: G11C7/1078 ,  G11C7/1084

Abstract: A semiconductor device stabilizes an operation of an input buffer. A semiconductor device includes an input potential detection unit, an input buffer, and a current sink unit. The input potential detection unit outputs a detection signal in response to a level of an input signal. The input buffer buffers the input signal by differentially amplifying the input signal through a first current sink unit. The current sink unit receives the detection signal, and in response to the detection signal, performs an auxiliary differential amplifying operation with respect to the input signal buffered by the input buffer.

Abstract translation: 半导体器件稳定输入缓冲器的操作。 半导体器件包括输入电位检测单元，输入缓冲器和电流吸收单元。 输入电位检测单元响应于输入信号的电平输出检测信号。 输入缓冲器通过第一电流吸收单元对输入信号进行差分放大来缓冲输入信号。 当前的接收单元接收检测信号，并且响应于检测信号，对由输入缓冲器缓冲的输入信号执行辅助差分放大操作。