公开(公告)号：US07521348B2

公开(公告)日：2009-04-21

申请号：US11871877

申请日：2007-10-12

Applicant: Sung-Hyun Kwon ,  Jae-Hwang Sim ,  Dong-Hwa Kwak ,  Joo-Young Kim

Inventor： Sung-Hyun Kwon ,  Jae-Hwang Sim ,  Dong-Hwa Kwak ,  Joo-Young Kim

IPC: H01L21/44

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A method for fabricating a semiconductor device having fine contact holes is exemplarily disclosed. The method includes forming an isolation layer defining active regions on a semiconductor substrate. An interlayer dielectric layer is formed on the semiconductor substrate having the isolation layer. First molding patterns are formed on the interlayer dielectric layer. Second molding patterns positioned between the first molding patterns and spaced apart therefrom are also formed. A mask pattern surrounding sidewalls of the first and second molding patterns is formed. Openings are formed by removing the first and second molding patterns. Contact holes are formed by etching the interlayer dielectric layer using the mask pattern as an etching mask.

Abstract translation: 示例性地公开了一种制造具有精细接触孔的半导体器件的方法。 该方法包括在半导体衬底上形成限定有源区的隔离层。 在具有隔离层的半导体衬底上形成层间电介质层。 在层间电介质层上形成第一成型图案。 还形成了位于第一模制图案之间并与之间隔开的第二模制图案。 形成围绕第一和第二模制图案的侧壁的掩模图案。 通过去除第一和第二模制图案形成开口。 通过使用掩模图案作为蚀刻掩模蚀刻层间电介质层来形成接触孔。

公开(公告)号：US20140167290A1

公开(公告)日：2014-06-19

申请号：US14186617

申请日：2014-02-21

Applicant: Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

Inventor： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

IPC: H01L23/528

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

Abstract translation: 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。

公开(公告)号：US20110136340A1

公开(公告)日：2011-06-09

申请号：US12904363

申请日：2010-10-14

Applicant: Jae-Hwang Sim ,  Yoon-Moon PARK ,  Keon-Soo KIM ,  Min-Sung SONG ,  Young-Ho LEE

Inventor： Jae-Hwang Sim ,  Yoon-Moon PARK ,  Keon-Soo KIM ,  Min-Sung SONG ,  Young-Ho LEE

IPC: H01L21/3213 ,  H01L21/308

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  Y10S438/947

Abstract: A method of fabricating a semiconductor device facilitates the forming of a conductive pattern of features having different widths. A conductive layer is formed on a substrate, and a mask layer is formed on the conductive layer. First spaced apart patterns are formed on the mask layer and a second pattern including first and second parallel portion is formed beside the first patterns on the mask layer. First auxiliary masks are formed over ends of the first patterns, respectively, and a second auxiliary mask is formed over the second pattern as spanning the first and second portions of the second pattern. The mask layer is then etched to form first mask patterns below the first patterns and a second mask pattern below the second pattern. The first and second patterns and the first and second auxiliary masks are removed. The conductive layer is then etched using the first and second mask patterns as an etch mask.

Abstract translation: 制造半导体器件的方法有助于形成具有不同宽度的特征的导电图案。 在基板上形成导电层，在导电层上形成掩模层。 在掩模层上形成第一间隔开的图案，并且在掩模层上的第一图案旁边形成包括第一和第二平行部分的第二图案。 第一辅助掩模分别形成在第一图案的端部上，并且第二辅助掩模形成在第二图案上，跨越第二图案的第一和第二部分。 然后蚀刻掩模层以在第一图案下方形成第一掩模图案，并在第二图案下方形成第二掩模图案。 去除第一和第二图案以及第一和第二辅助掩模。 然后使用第一和第二掩模图案作为蚀刻掩模蚀刻导电层。

公开(公告)号：US20110032763A1

公开(公告)日：2011-02-10

申请号：US12909223

申请日：2010-10-21

Applicant: Dong-Hwa Kwak ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Jin-Ho Kim ,  Ki-Nam Kim

Inventor： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Jin-Ho Kim ,  Ki-Nam Kim

IPC: G11C16/04

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

Abstract: In some embodiments, a semiconductor device includes first bit lines connected to respective first contacts. Spacers are disposed on sidewalls of the first bit lines. A second bit line is self-alignedly disposed between adjacent spacers, and a second contact is self-aligned with and connected to the second bit line.

Abstract translation: 在一些实施例中，半导体器件包括连接到相应的第一触点的第一位线。 间隔件设置在第一位线的侧壁上。 第二位线自相对地布置在相邻间隔件之间，并且第二触点与第二位线自对准并连接到第二位线。

公开(公告)号：US20090305495A1

公开(公告)日：2009-12-10

申请号：US12465013

申请日：2009-05-13

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/31144

Abstract: A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.

Abstract translation: 半导体器件可以包括以锯齿形图案布置的插塞，电连接到插头的互连和插入在插头和互连之间的保护图案以选择性地暴露插头。 互连可以包括与由保护图案选择性地暴露的插头接触的连接部分。 制造半导体器件的方法包括：在形成模制图案和掩模图案之后，使用掩模图案选择性地蚀刻保护层以形成露出插头的保护图案。

公开(公告)号：US08686563B2

公开(公告)日：2014-04-01

申请号：US12639542

申请日：2009-12-16

Applicant: Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

Inventor： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

Abstract translation: 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。

公开(公告)号：US08680602B2

公开(公告)日：2014-03-25

申请号：US13412863

申请日：2012-03-06

Applicant: Jae-Hwang Sim ,  Jae-Bok Baek

Inventor： Jae-Hwang Sim ,  Jae-Bok Baek

IPC: H01L29/788 ,  H01L29/76 ,  H01L21/70 ,  H01L27/108 ,  H01L29/94 ,  H01L21/336 ,  H01L21/76 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/28 ,  H01L21/28273 ,  H01L21/764 ,  H01L27/11529 ,  H01L27/11546 ,  H01L29/7881

Abstract: A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point.

Abstract translation: 半导体器件包括：衬底，包括第一区域和第二区域;栅极组，设置在衬底的第一区域中，栅极组包括多个单元栅极图案和至少一个选择栅极图案，第一栅极图案布置 在衬底的第二区域中，覆盖栅极组的顶表面和侧表面的组间隔件，具有第一拐点的组间隔件和覆盖第一栅极的顶表面和侧表面的第一图案间隔件 第一图案间隔物具有第二拐点。

公开(公告)号：US20130072022A1

公开(公告)日：2013-03-21

申请号：US13678930

申请日：2012-11-16

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

IPC: H01L21/311

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

Abstract translation: 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

公开(公告)号：US20120313159A1

公开(公告)日：2012-12-13

申请号：US13468552

申请日：2012-05-10

Applicant: Jae-Hwang Sim

Inventor： Jae-Hwang Sim

IPC: H01L29/792

CPC classification number: H01L21/28273 ,  H01L21/764 ,  H01L27/11529 ,  H01L29/42324 ,  H01L29/7881

Abstract: Non-volatile memory devices and methods of manufacturing the same are disclosed. In a non-volatile memory device, widths of a metal gate and an upper portion of a base gate in a gate electrode are less than the width of a hard mask pattern disposed on the metal gate. First and second protection spacers are disposed on opposing sidewalls of the metal gate and on opposing sidewalls of the upper portion of the base gate, respectively.

Abstract translation: 公开了非易失性存储器件及其制造方法。 在非易失性存储器件中，栅电极中的金属栅极和基极栅极的上部的宽度小于设置在金属栅极上的硬掩模图案的宽度。 第一和第二保护间隔物分别设置在金属栅极的相对的侧壁和基栅的上部的相对侧壁上。

公开(公告)号：US20120146125A1

公开(公告)日：2012-06-14

申请号：US13212639

申请日：2011-08-18

Applicant: Minchul Kim ,  Jae-Hwang Sim ,  Sangbin Song

Inventor： Minchul Kim ,  Jae-Hwang Sim ,  Sangbin Song

IPC: H01L29/788

CPC classification number: H01L21/32135 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/1157 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: A non-volatile memory device comprises a substrate, a control gate electrode on the substrate, and a charge storage region between the control gate electrode and the substrate. A control gate mask pattern is on the control gate electrode, the control gate electrode comprising a control base gate and a control metal gate on the control base gate. A width of the control metal gate is less than a width of the control gate mask pattern. An oxidation-resistant spacer is at sidewalls of the control metal gate positioned between the control gate mask pattern and the control base gate.

Abstract translation: 非易失性存储器件包括衬底，衬底上的控制栅极电极和控制栅电极与衬底之间的电荷存储区域。 控制栅极掩模图案位于控制栅电极上，控制栅极电极包括控制基极栅极和控制基极栅极上的控制金属栅极。 控制金属栅极的宽度小于控制栅极掩模图案的宽度。 位于控制栅掩模图案和控制基栅之间的控制金属栅极的侧壁处具有抗氧化间隔物。