公开(公告)号：US06248623B1

公开(公告)日：2001-06-19

申请号：US09439170

申请日：1999-11-12

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L28242

CPC分类号： H01L27/10894 ,  H01L21/823425 ,  H01L21/823468 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888

摘要： A method of manufacturing an embedded memory. A substrate has a memory cell region and a logic circuit region. A plurality of first gate structures and a plurality of second gate structures are respectively formed on the substrate in the memory cell region and the logic circuit region. Every space between the first gate structures is smaller than those between the second gate structures. A first spacer is formed over a sidewall of each first gate structure and over a sidewall of each second gate structure. Several lightly doped drain regions are formed in the substrate exposed by the first spacers and the second gate structures in the logic circuit region. A second spacer is formed on each first spacer in the logic circuit region and a silicide block is simultaneously formed to fill space between the first gate structures in the memory cell region. A source/drain region is formed in the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region. A silicide layer is formed on the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region.

摘要翻译： 一种制造嵌入式存储器的方法。 衬底具有存储单元区域和逻辑电路区域。 多个第一栅极结构和多个第二栅极结构分别形成在存储单元区域和逻辑电路区域中的衬底上。 第一栅极结构之间的每个空间都小于第二栅极结构之间的间隔。 在每个第一栅极结构的侧壁上并且在每个第二栅极结构的侧壁之上形成第一间隔物。 在由第一间隔物和逻辑电路区域中的第二栅极结构暴露的衬底中形成几个轻掺杂漏极区。 在逻辑电路区域中的每个第一间隔物上形成第二间隔物，同时形成硅化物块以填充存储单元区域中的第一栅极结构之间的空间。 源极/漏极区域形成在由第二间隔物暴露的衬底中，第一间隔物和第二栅极结构在逻辑电路区域中。 在由第二间隔物暴露的衬底上形成硅化物层，在逻辑电路区域中形成第一间隔物和第二栅极结构。

公开(公告)号：US6110827A

公开(公告)日：2000-08-29

申请号：US655074

申请日：1996-06-03

申请人： Sun-Chieh Chien ,  Der-Yuan Wu ,  Kun-Cho Chen

发明人： Sun-Chieh Chien ,  Der-Yuan Wu ,  Kun-Cho Chen

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/76819 ,  Y10S438/959

摘要： A planarization method for self-aligned contact process which is suitable for use in DRAM processing. Prior to the formation of the bottom terminal layer of the capacitor, the substrate surface is first planarized, thus avoiding stringer effects and related bridging problems arising from an undulating surface profile, during subsequent etching of the defined pattern. Also according to the method of this invention, by covering the silicon substrate that has MOS transistors laid on top with first a deposition of an oxide layer, then an etch discriminatory layer, and finally a planarization layer, a substrate with a smooth, plane surface is obtained.

摘要翻译： 用于自对准接触工艺的平面化方法，适用于DRAM处理。 在形成电容器的底部端子层之前，首先将衬底表面平坦化，从而在随后蚀刻限定的图案期间避免由起伏的表面轮廓引起的纵梁效应和相关的桥接问题。 此外，根据本发明的方法，首先通过覆盖首先沉积氧化物层的MOS晶体管的硅衬底，然后蚀刻鉴别层，最后是平坦化层，具有平滑的平面表面的衬底 获得。

公开(公告)号：US5874334A

公开(公告)日：1999-02-23

申请号：US8900

申请日：1998-01-20

申请人： Jason Jenq ,  Sun-Chieh Chien

发明人： Jason Jenq ,  Sun-Chieh Chien

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/40

摘要： A method for fabricating a DRAM capacitor comprising the steps of forming silicon nitride spacers twice, not only serving as etching stop layer in a self-aligned contact etching process, but also used as a protective layer for the bit line and gate electrode in an etching operation. In another aspect, using silicon nitride spacers has the advantage of being capable of increasing the width of a contact opening. Hence, a contact opening having a smaller height to width ratio can be produced. Furthermore, the lower electrode of the capacitor in this invention is a pillar-shaped structure, and together with the formation of a hemispherical grained silicon layer over the lower electrode, the surface area of the capacitor can be greatly increased. Moreover, a dielectric layer having a high dielectric constant can be used; hence, a capacitor with sufficient capacitance can be provided although the surface area of the storage capacitor is reduced.

摘要翻译： 一种用于制造DRAM电容器的方法，包括以下步骤：形成氮化硅间隔物两次，不仅用作自对准接触蚀刻工艺中的蚀刻停止层，而且还用作蚀刻中的位线和栅电极的保护层 操作。 在另一方面，使用氮化硅间隔物具有能够增加接触开口的宽度的优点。 因此，可以制造具有较小高度与宽度比的接触开口。 此外，本发明的电容器的下部电极为柱状结构，并且在下部电极上形成半球状的硅层，能够大幅提高电容器的表面积。 此外，可以使用具有高介电常数的介电层; 因此，尽管存储电容器的表面积减小，但是可以提供具有足够电容的电容器。

公开(公告)号：US5624870A

公开(公告)日：1997-04-29

申请号：US405489

申请日：1995-03-16

申请人： Sun-Chieh Chien ,  Yu-Ju Liu

发明人： Sun-Chieh Chien ,  Yu-Ju Liu

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76838 ,  H01L21/7684

摘要： A method of planarizing an electrical contact region in a silicon substrate uses spin-on-glass or polysilicon as plug material (42) to fill a contact hole (34). A device or doped region (31) is formed at the surface of the substrate (30) and an insulating layer (33) is formed over the substrate so that the entire doped region is covered by the insulating layer. The contact hole is then formed through the insulating layer to expose a portion of the doped region. To increase the conductivity of the doped region through the contact hole, a filler layer of either spin-on-glass or polysilicon, thick enough to substantially fill the contact hole, is formed over the insulating layer. The filler layer is then etched away from the portions around the contact hole by a conventional dry or wet oxide etching process.

摘要翻译： 平面化硅衬底中的电接触区域的方法使用旋涂玻璃或多晶硅作为插塞材料（42）填充接触孔（34）。 在衬底（30）的表面上形成器件或掺杂区域（31），并且在衬底上形成绝缘层（33），使得整个掺杂区域被绝缘层覆盖。 然后通过绝缘层形成接触孔以暴露掺杂区域的一部分。 为了增加通过接触孔的掺杂区的导电性，在绝缘层上形成厚度足以基本上填充接触孔的旋涂玻璃或多晶硅的填充层。 然后通过常规的干或湿氧化物蚀刻工艺将填料层从接触孔周围的部分蚀刻掉。

公开(公告)号：US5521113A

公开(公告)日：1996-05-28

申请号：US405078

申请日：1995-03-16

申请人： Chen-Chiu Hsue ,  Sun-Chieh Chien

发明人： Chen-Chiu Hsue ,  Sun-Chieh Chien

IPC分类号： H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S148/02

摘要： An SRAM cell includes a semiconductor substrate doped with a dopant of a first type, a highly doped region in the substrate implanted with a dopant of opposite type, a gate oxide layer on the substrate, a first conductive layer formed upon the gate oxide layer, a dielectric layer deposited over the first conductive layer, an opening in the gate oxide layer, the first conductive layer, and the dielectric layer, and a second conductive layer deposited upon the dielectric layer.

摘要翻译： SRAM单元包括掺杂有第一类型的掺杂剂的半导体衬底，注入相反类型的掺杂剂的衬底中的高度掺杂区域，衬底上的栅极氧化物层，形成在栅极氧化物层上的第一导电层， 沉积在第一导电层上的电介质层，栅极氧化物层中的开口，第一导电层和介电层，以及沉积在电介质层上的第二导电层。

公开(公告)号：US5413953A

公开(公告)日：1995-05-09

申请号：US315706

申请日：1994-09-30

申请人： Sun-Chieh Chien ,  Ming-Hua Liu

发明人： Sun-Chieh Chien ,  Ming-Hua Liu

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/768 ,  H01L21/76

CPC分类号： H01L21/76213 ,  H01L21/31053 ,  H01L21/76819

摘要： An improved process for fabricating a planar field oxide structure on a silicon substrate was achieved. The process involves forming the field oxide by using the LOCal Oxidation of Silicon (LOCOS) process in which the device area is protected from oxidation by a silicon nitride layer. A sacrificial implant layer, such as CVD oxide, oxynitride or an anti-reflective coating (ARC) layer is used to fill in the gap between the silicon nitride and the field oxide structure and make more planar the substrate surface. The substrate surface is then implanted with As.sup.75 or p.sup.31 ions penetrating the sacrificial implant layer and forming a implant damaged layer on the field oxide. The implant damaged layer which etches faster in a wet etch in removed selectively thereby making a more planar field oxide structure. The method does not require a recess to be etched in the silicon substrate and therefore, has certain reliability and cost advantages. The invention also describes a method for forming more gradually sloping steps on the field oxide structure without using a sacrificial layer and a method for planarizing a CVD over a patterned conducting layer using photoresist or spin-on-glass as the sacrificial implant layer.

摘要翻译： 实现了在硅衬底上制造平面场氧化物结构的改进方法。 该方法包括通过使用硅的LOCal氧化（LOCOS）工艺形成场氧化物，其中器件区域被氮化硅层防止氧化。 使用诸如CVD氧化物，氧氮化物或抗反射涂层（ARC）层的牺牲注入层来填充氮化硅和场氧化物结构之间的间隙，并使衬底表面更平坦。 然后将衬底表面注入穿过牺牲注入层的As75或p31离子，并在场氧化物上形成植入物损伤层。 在湿蚀刻中蚀刻更快的植入物损伤层选择性地移除，从而形成更平坦的场氧化物结构。 该方法不需要在硅衬底中蚀刻凹槽，因此具有一定的可靠性和成本优点。 本发明还描述了一种用于在不使用牺牲层的情况下在场氧化物结构上形成更多逐渐倾斜的步骤的方法，以及使用光致抗蚀剂或旋涂玻璃作为牺牲注入层在图案化导电层上平坦化CVD的方法。

公开(公告)号：US06733597B2

公开(公告)日：2004-05-11

申请号：US09841817

申请日：2001-04-24

申请人： Chih-Ning Wu ,  Sun-Chieh Chien

发明人： Chih-Ning Wu ,  Sun-Chieh Chien

IPC分类号： B08B300

CPC分类号： H01L21/76814 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76838 ,  Y10S134/902 ,  Y10S438/906

摘要： A method is provided for cleaning a dual damascene structure. A first metal layer, a cap layer, and a dielectric layer are formed on a substrate in sequence. Then a dual damascene opening is formed in the dielectric layer and the cap layer exposing the first metal layer. Next, a post-etching cleaning step is carried out to clean the dual damascene opening using a fluorine-based solvent. Then, an argon gas plasma is sputtered to clean the dual damascene opening before a second metal layer fills in the dual damascene opening.

摘要翻译： 提供了一种清洗双镶嵌结构的方法。 依次在基板上形成第一金属层，盖层和电介质层。 然后在电介质层中形成双镶嵌开口，并且覆盖层露出第一金属层。 接下来，进行后蚀刻清洗工序，使用氟系溶剂清洗双镶嵌开口。 然后，在第二金属层填充到双镶嵌开口之前，溅射氩气等离子体以清洁双镶嵌开口。

公开(公告)号：US06692580B2

公开(公告)日：2004-02-17

申请号：US10407626

申请日：2003-04-04

申请人： Chih-Ning Wu ,  Sun-Chieh Chien

发明人： Chih-Ning Wu ,  Sun-Chieh Chien

IPC分类号： B08B300

CPC分类号： H01L21/76814 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76838 ,  Y10S134/902 ,  Y10S438/906

摘要： A method of cleaning a dual damascene structure. A first metal layer, a cap layer, and a dielectric layer are formed on a substrate in sequence. Then a dual damascene opening is formed in the dielectric layer and the cap layer, exposing the first metal layer. Then, a post-etching cleaning step is carried out to clean the dual damascene opening, and there are two types of cleaning methods. The first method uses a fluorine-based solvent to clean the dual damascene opening. An alternative cleaning method uses a hydrogen peroxide based solvent at a high temperature, followed by a hydrofluoric acid solvent cleaning step. Then, an argon gas plasma is sputtered to clean the dual damascene opening before a second metal layer fills in the dual damascene opening.

摘要翻译： 一种清洗双镶嵌结构的方法。 依次在基板上形成第一金属层，盖层和电介质层。 然后在电介质层和盖层中形成双镶嵌开口，露出第一金属层。 然后，执行后蚀刻清洁步骤以清洁双镶嵌开口，并且存在两种类型的清洁方法。 第一种方法使用氟类溶剂清洗双镶嵌开口。 另一种清洗方法是在高温下使用基于过氧化氢的溶剂，然后使用氢氟酸溶剂清洗步骤。 然后，在第二金属层填充到双镶嵌开口之前，溅射氩气等离子体以清洁双镶嵌开口。

公开(公告)号：US06559059B2

公开(公告)日：2003-05-06

申请号：US09764327

申请日：2001-01-19

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L2100

CPC分类号： H01L27/10894 ,  H01L21/82345 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10873

摘要： The present invention provides a method of manufacturing a MOS transistor of an embedded memory. The method of the present invention involves first defining a memory array area and a periphery circuit region on the surface of the semiconductor wafer and to deposit a gate oxide layer, an undoped polysilicon layer and a dielectric layer, respectively. Next, the undoped polysilicon layer in the memory array area is implanted to form a doped polysilicon layer followed by the removal of the dielectric layer in the memory array area. Thereafter, a metallic silicide layer and a passivation layer are formed, respectively, on the surface of the semiconductor wafer. The passivation layer, the metallic silicide layer and the doped polysilicon layer are then etched to form a plurality of gates in the memory array area. Next, the passivation layer, the metallic silicide layer and the dielectric layer in the periphery circuit region are removed. Finally, the undoped polysilicon layer is etched to form a plurality of gates in the periphery circuit region, followed by the formation of spacers, sources and drains of each MOS transistors, respectively, in the periphery circuit region.

公开(公告)号：US06509223B2

公开(公告)日：2003-01-21

申请号：US09764334

申请日：2001-01-19

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L218238

CPC分类号： H01L21/82345 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894

摘要： The present invention provides a method for forming an embedded memory MOS. The method involves first forming a first dielectric layer and an undoped polysilicon layer, respectively, on the surface of the semiconductor wafer with a defined memory array area and a periphery circuits region. Then, the undoped polysilicon layer in the memory array area is doped to become a doped polysilicon layer, followed by the formation of a protective layer on the surface of the semiconductor wafer. Thereafter, a first photolithographic and etching process(PEP) is used to etch the protective layer and the doped polysilicon layer in the memory array area to form a plurality of gates, and to form lightly doped drains(LDD) adjacent to each gate. A silicon nitride layer and a second dielectric layer are formed, followed by their removal in the periphery circuits region. Finally, a second PEP is used to etch the undoped polysilicon layer in the periphery circuits region to form a plurality of gates, as well as to form LDDs, spacers and sources/drains(S/D) of each MOS in the periphery circuits region.

摘要翻译： 本发明提供一种形成嵌入式存储器MOS的方法。 该方法包括首先在具有限定的存储器阵列区域和外围电路区域的半导体晶片的表面上分别形成第一电介质层和未掺杂的多晶硅层。 然后，将存储器阵列区域中的未掺杂多晶硅层掺杂成为掺杂多晶硅层，随后在半导体晶片的表面上形成保护层。 此后，使用第一光刻和蚀刻工艺（PEP）来蚀刻存储器阵列区域中的保护层和掺杂多晶硅层以形成多个栅极，并且形成与每个栅极相邻的轻掺杂漏极（LDD）。 形成氮化硅层和第二电介质层，然后在外围电路区域中除去。 最后，使用第二PEP来蚀刻外围电路区域中的未掺杂的多晶硅层以形成多个栅极，并且在外围电路区域中形成每个MOS的LDD，间隔物和源极/漏极（S / D） 。