公开(公告)号：US06313688B1

公开(公告)日：2001-11-06

申请号：US09709315

申请日：2000-11-13

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： G06F744

CPC分类号： H04B1/40 ,  H03D7/1441 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/403

摘要： A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node. Preferably, each of the plurality of switches includes two pairs of serially connected transistors, wherein the serially connected transistors are coupled in parallel to provide a symmetric electrical connection for each of two input ports. The mixer and method for using same can be single or double-balanced mixers receiving an RF input signal.

摘要翻译： 根据本发明的混合器结构及其使用方法包括多相混合器。 VCO包括多个差分延迟单元，以输出多个多相时钟信号。 多相混频器可以包括负载电路，开关电路，降噪电路和输入电路。 开关电路被耦合以接收多个多相时钟信号，并且包括分别耦合到负载电路的第一开关阵列和第二开关阵列。 耦合到开关电路的降噪电路可以包括响应偏置电压的晶体管。 输入电路包括接收输入信号的晶体管。 第一开关阵列包括耦合在第一输出端子和第二节点之间的第一多个开关，并且第二开关阵列包括耦合在第二输出端子和第二节点之间的第二多个开关。 优选地，多个开关中的每一个包括两对串联连接的晶体管，其中串联连接的晶体管并联耦合以为两个输入端口中的每一个提供对称电连接。 混频器和使用它的方法可以是接收RF输入信号的单或双平衡混频器。

公开(公告)号：US5905769A

公开(公告)日：1999-05-18

申请号：US646450

申请日：1996-05-07

申请人： Kyeongho Lee ,  Deog-Kyon Jeong

发明人： Kyeongho Lee ,  Deog-Kyon Jeong

IPC分类号： H04L7/00 ,  H04L7/033 ,  H04L7/04 ,  H04N7/083 ,  H04N7/52 ,  H04N21/2368 ,  H04N21/434 ,  H03D3/24

CPC分类号： H04N7/52 ,  H04L7/0337 ,  H04N21/4305 ,  H04N7/083 ,  H04L2007/045 ,  H04L7/0008

摘要： A method and apparatus is disclosed that receives a multi-channel digital serial encoded signal and converting it signal into a synchronized set of binary characters. A charge pump phase-locked loop receives a transmitted reference clock and derives a multi-phase clock from the reference clock. The multi-phase clock is used to control a plurality of multi-bit block assembly circuits. Each assembly circuit receives one channel of the digital signal and produces a multi-bit block or character. The multi-bit block assembly circuit includes an oversampler, a digital phase-locked loop and a byte synchronizer. The oversampler oversamples the received digital signal under control of the multiphase clock and produces a sequence of oversampled binary data. The digital phase-locked loop receives the oversampled data and selects samples from it depending on the skew characteristics of the sample. The byte synchronizer assembles a sequence of selected bits into a bit block, or character. An interchannel synchronizer receives as input the characters produced by each of the multi-bit block assembly circuits, and selectively delays output of the received characters in order to synchronize the characters of each channel with one another.

摘要翻译： 公开了一种接收多通道数字串行编码信号并将其转换成同步的二进制字符集的方法和装置。 电荷泵锁相环接收传输的参考时钟并从参考时钟导出多相时钟。 多相时钟用于控制多个多位块组合电路。 每个汇编电路接收数字信号的一个通道并产生多位块或字符。 多比特块组合电路包括过采样器，数字锁相环和字节同步器。 过采样器在多相时钟的控制下对接收到的数字信号进行过采样，并产生过采样二进制数据序列。 数字锁相环接收过采样数据，并根据样本的偏斜特性从中选择样本。 字节同步器将选定位的序列组合成位块或字符。 通道间同步器接收由多位块组合电路中的每一个产生的字符作为输入，并且选择性地延迟所接收字符的输出，以便使每个通道的字符彼此同步。

公开(公告)号：US5815041A

公开(公告)日：1998-09-29

申请号：US631420

申请日：1996-04-12

申请人： Kyeongho Lee ,  Deog-kyoon Jeong

发明人： Kyeongho Lee ,  Deog-kyoon Jeong

IPC分类号： H03K5/26 ,  H03L7/089 ,  H03K5/13

CPC分类号： H03L7/0891

摘要： A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively. The up signal generator includes a first p field effect transistor (FET) having a gate for receiving a set signal, a second p FET having a source coupled to the drain of the first p FET and having a gate for receiving a reference clock signal. A first n FET has a source coupled to the drain of the second p FET and has a gate for receiving the set signal. A third p FET has a gate coupled to the drain of the second p FET. A second n FET has a source coupled to the drain of the third p FET for providing the up signal, and has a gate for receiving the reference clock signal. A third n FET has a source coupled to the drain of the second n FET and has a gate coupled to the gate of the third p FET. The down signal generator includes a fourth p FET having a gate for receiving the set signal. A fifth p FET has a source coupled to the drain of the fourth p FET and has a gate for receiving a VCO clock signal. A fourth n FET has a source coupled to the drain of the fifth n FET and has a gate for receiving the set signal. A sixth p FET has a gate coupled to the drain of the fifth p FET. A fifth n FET has a source coupled to the drain of the sixth p FET and has a gate for receiving the VCO clock signal. A sixth n FET has a source coupled to the drain of the fifth n FET for providing the down signal, and has a gate coupled to the gate of the sixth p FET. A reset circuit, such as a NAND gate, has a first input coupled to the drain of the third p PET, has a second input coupled to the drain of the sixth p FET, and has an output for generating the set signal.

公开(公告)号：US07952442B2

公开(公告)日：2011-05-31

申请号：US11274825

申请日：2005-11-16

申请人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H03B5/12

CPC分类号： H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.

摘要翻译： 集成电路封装包括由接合线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感环路。 在一个实施例中，电感环由将集成电路芯片上的焊盘连接到封装的I / O引脚的第一布线和将相同的焊盘连接到同一引脚的第二布线形成。 通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。

公开(公告)号：US20080252377A1

公开(公告)日：2008-10-16

申请号：US11976911

申请日：2007-10-29

申请人： Seung-Wook Lee ,  Deok Hee Lee ,  Eunseok Song ,  Joonbae Park ,  Kyeongho Lee

发明人： Seung-Wook Lee ,  Deok Hee Lee ,  Eunseok Song ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H03G3/30 ,  H04B1/16

CPC分类号： H03F1/223 ,  H03F3/193 ,  H03F2200/372

摘要： Embodiments of the present general inventive concept include a low noise amplifier and method with an improved linearity while reducing a noise disadvantage (e.g., increase). One embodiment of a low noise amplifier can include a first transistor to receive an input signal at a control terminal thereof, a second transistor having a first terminal coupled to a second terminal of the first transistor, an envelope detector to output a control signal corresponding to a characteristic of the input signal and an envelope amplifier to amplify the control signal to be applied to a control terminal of the second transistor.

摘要翻译： 本发明总体构思的实施例包括具有改善的线性度的低噪声放大器和方法，同时降低噪声不利（例如增加）。 低噪声放大器的一个实施例可以包括在其控制端接收输入信号的第一晶体管，具有耦合到第一晶体管的第二端的第一端的第二晶体管，用于输出对应于 输入信号的特性和包络放大器，放大要施加到第二晶体管的控制端的控制信号。

公开(公告)号：US20080139161A1

公开(公告)日：2008-06-12

申请号：US11819943

申请日：2007-06-29

申请人： Joonbae Park ,  Kyeongho Lee ,  Sang Hun Jung ,  Eal Wan Lee ,  In Ho Song

发明人： Joonbae Park ,  Kyeongho Lee ,  Sang Hun Jung ,  Eal Wan Lee ,  In Ho Song

IPC分类号： H04B1/26

CPC分类号： H04L27/0014 ,  H04L2027/0016 ,  H04L2027/0022

摘要： The application discloses embodiments of methods and/or systems for compensating a transmission carrier leakage of an up-conversion mixer, a tranceiving circuit or apparatus embodying the same. One embodiment of a method can include detecting an I channel DC offset DCI0 and a Q channel DC offset DCQ0 generated by a reception carrier leakage from an output of a down-conversion mixer, detecting an I channel DC offset DCI and a Q channel DC offset DCQ from the output of the down-conversion mixer while varying a compensation parameter being inputted to an up-conversion mixer that has its output coupled to an input of the down-conversion mixer to determine the compensation parameter that can reduce or minimize a transmission carrier leakage. A combination of a transmission baseband signal and the determined compensation parameter can be transmitted using the up-conversion mixer and an antenna to compensate for the transmission carrier leakage.

摘要翻译： 本申请公开了用于补偿上变频混频器，引入电路或体现其的转换电路或设备的传输载波泄漏的方法和/或系统的实施例。 方法的一个实施例可以包括从下行链路的输出检测由接收载波泄漏产生的I信道DC偏移DCI 0和Q信道DC偏移DCQ <0> 转换混频器，从下转换混频器的输出端检测I信道DC偏移DCI和Q信道DC偏移DCQ，同时改变输入到上变频混频器的补偿参数，该上变频混频器的输出耦合到下变频混频器的输入 转换混频器来确定可以减少或最小化传输载波泄漏的补偿参数。 传输基带信号和所确定的补偿参数的组合可以使用上变频混频器和天线来传输，以补偿传输载波泄漏。

公开(公告)号：US07202741B2

公开(公告)日：2007-04-10

申请号：US11066546

申请日：2005-02-28

申请人： Joonbae Park ,  Seung-Wook Lee ,  Jeong-Woo Lee ,  Kyeongho Lee

发明人： Joonbae Park ,  Seung-Wook Lee ,  Jeong-Woo Lee ,  Kyeongho Lee

IPC分类号： H03F3/45

CPC分类号： H03F3/211 ,  H03F3/45475 ,  H03F3/45659 ,  H03F2203/45136 ,  H03F2203/45138 ,  H03F2203/45166 ,  H03F2203/45168 ,  H03F2203/45434 ,  H03F2203/45522 ,  H03F2203/45591

摘要： A variable-gain amplifier circuit uses a pair of single-ended operational amplifiers to amplify complementary portions of a differential input signal. By using two single-ended amplifiers instead of a single differential amplifier, linearity is significantly improved. In addition, common mode feedback circuitry is eliminated along with harmonic distortion and other forms of noise which tend to negative affect the quality of the signal output from the circuit.

摘要翻译： 可变增益放大器电路使用一对单端运算放大器来放大差分输入信号的互补部分。 通过使用两个单端放大器而不是单个差分放大器，线性度显着提高。 此外，消除共模反馈电路以及谐波失真和其他形式的噪声，这些噪声倾向于负面影响从电路输出的信号的质量。

公开(公告)号：US20070015479A1

公开(公告)日：2007-01-18

申请号：US11272053

申请日：2005-11-14

申请人： Joonbae Park ,  Seung Lee ,  Jeong Lee ,  Kyeongho Lee

发明人： Joonbae Park ,  Seung Lee ,  Jeong Lee ,  Kyeongho Lee

IPC分类号： H04B1/18

CPC分类号： H04B1/28 ,  H04B1/30

摘要： A wireless receiver and a wireless receiving method are provided wherein a frequency of a radio frequency (RF) is down-converted into a frequency of a substantially zero intermediate frequency (IF) signal or a substantially low IF signal. The down-converted signal may be filtered by an integrated filter having a low quality factor and then up-converted again into a particular IF signal, thereby integrating an external element. For example, a receiving device may receive a RF signal in a required band. A frequency down-converting device may down-convert a frequency so that a center frequency of the RF signal becomes zero. A channel select filtering device may select a required channel from the signals whose frequency is down-converted. An IF signal converting device may up-convert a frequency of the channel selected signal into a required IF. An IF processing device may extract a baseband signal after the converted IF signal is inputted and processed. An amplifying device may amplify a signal with a gain required in a process of converting a frequency.

摘要翻译： 提供了一种无线接收机和无线接收方法，其中射频（RF）的频率被下变频成基本为零的中频（IF）信号或基本上低的IF信号的频率。 下变频信号可以由具有低质量因子的积分滤波器滤波，然后再次上变频成特定的IF信号，从而整合外部元件。 例如，接收设备可以接收所需频带中的RF信号。 降频转换装置可以降频转换频率，使得RF信号的中心频率变为零。 频道选择滤波装置可以从频率被下变频的信号中选择所需频道。 IF信号转换装置可以将频道选择信号的频率上变频成所需的IF。 IF处理装置可以在转换的IF信号被输入和处理之后提取基带信号。 放大装置可以放大具有在转换频率的过程中所需的增益的信号。

公开(公告)号：US07035351B1

公开(公告)日：2006-04-25

申请号：US09705696

申请日：2000-11-06

申请人： Joonbae Park ,  Wonchan Kim ,  Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Joonbae Park ,  Wonchan Kim ,  Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03D3/18

CPC分类号： H04B1/30 ,  H03F3/211 ,  H03F2200/294 ,  H03F2200/372

摘要： A DC offset cancelling circuit with multiple feedback loops suppresses DC offset voltages within an automatic gain control loop apparatus. The apparatus includes a plurality of gain stages connected in series that receive and amplify an input RF signal. Each gain stage includes a corresponding feedback loop to filter the DC offset voltage accumulated in the respective gain stage.

摘要翻译： 具有多个反馈环路的DC偏移消除电路抑制自动增益控制环路装置内的DC偏移电压。 该装置包括串联连接的多个增益级，其接收和放大输入RF信号。 每个增益级包括相应的反馈回路以对累积在相应增益级中的DC偏移电压进行滤波。

公开(公告)号：US20060081973A1

公开(公告)日：2006-04-20

申请号：US11274825

申请日：2005-11-16

申请人： Yido Koo ,  Hyungki Huh ,  Kang Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Yido Koo ,  Hyungki Huh ,  Kang Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H01L23/52

CPC分类号： H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.

摘要翻译： 集成电路封装包括由接合线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感环路。 在一个实施例中，电感环由将集成电路芯片上的焊盘连接到封装的I / O引脚的第一布线和将相同的焊盘连接到同一引脚的第二布线形成。 通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。