公开(公告)号：US06291252B1

公开(公告)日：2001-09-18

申请号：US09345175

申请日：1999-06-30

申请人： Allen S. Yu ,  Paul J. Steffan

发明人： Allen S. Yu ,  Paul J. Steffan

IPC分类号： H01L2100

CPC分类号： H01L21/67276 ,  Y10T29/41

摘要： A method of manufacturing semiconductor wafers in a processing tool in which it is determined whether the tool has been on idle beyond a predetermined period of time. If the tool has not been on idle beyond the predetermined period of time, a product wafer is automatically processed. If the tool has been on idle beyond the predetermined period of time, a conditioning wafer is automatically processed.

摘要翻译： 一种在处理工具中制造半导体晶片的方法，其中确定工具是否已经在预定时间段之后空转。 如果工具在预定时间之后没有闲置，则产品晶片被自动处理。 如果工具在预定时间段之后已经空转，则调节晶片被自动处理。

公开(公告)号：US06274443B1

公开(公告)日：2001-08-14

申请号：US09162116

申请日：1998-09-28

申请人： Allen S. Yu ,  Patrick K. Cheung ,  Paul J. Steffan

发明人： Allen S. Yu ,  Patrick K. Cheung ,  Paul J. Steffan

IPC分类号： H01L21336

CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L21/28123 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6659

摘要： An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles. Since the LDD structures are spaced away from the edges of the second polysilicon gates, the lateral diffusion of the LDD structures into the channel due to rapid thermal annealing is reduced.

摘要翻译： 通过在半导体衬底上形成栅氧化层，制造具有逐渐掺杂分布和降低工艺复杂度的LDD结构的超大规模CMOS集成电路半导体器件; 在所述栅极氧化物层上形成多晶硅层; 在所述多晶硅层上形成第一掩模层; 图案化和蚀刻第一掩模层以形成第一栅极掩模; 各向异性地蚀刻所述多晶硅层以形成第一多晶硅栅极，其中所述第一多晶硅栅极具有具有倾斜轮廓的侧壁，并且所述倾斜轮廓在所述LDD结构的离子注入期间用作掩模，以使所得到的LDD结构远离所述第二多晶硅的边缘 随后将形成具有基本垂直轮廓的多晶硅栅极。 由于LDD结构与第二多晶硅栅极的边缘间隔开，所以LDD结构由于快速热退火而向沟道中的横向扩散减小。

公开(公告)号：US06239008B1

公开(公告)日：2001-05-29

申请号：US09407907

申请日：1999-09-29

申请人： Allen S. Yu ,  Paul J. Steffan ,  Thomas C. Scholer

发明人： Allen S. Yu ,  Paul J. Steffan ,  Thomas C. Scholer

IPC分类号： H01L213205

CPC分类号： H01L21/3081 ,  H01L21/0274 ,  H01L21/0277 ,  H01L21/0278 ,  H01L21/0332

摘要： A method of manufacturing a semiconductor device with increased density of structures that have at least one dimension less than that provided by the lithography system being used in the manufacturing process.

摘要翻译： 制造具有比制造工艺中使用的光刻系统所提供的尺寸小至少一个尺寸的结构密度增加的半导体器件的方法。

公开(公告)号：US06191036B1

公开(公告)日：2001-02-20

申请号：US09290354

申请日：1999-04-12

申请人： Allen S. Yu ,  Paul J. Steffan ,  Bharath Rangarajan

发明人： Allen S. Yu ,  Paul J. Steffan ,  Bharath Rangarajan

IPC分类号： H01L21302

CPC分类号： G03F7/70625 ,  G03F7/70641 ,  H01L21/76802 ,  H01L22/34

摘要： A method of predicting etch efficacy of vias in a semiconductor manufacturing process wherein a photo focus exposure matrix (FEM) array is used as a via etch monitor. The FEM is an array of matrices wherein each array has a different size set of vias. The matrices in the array start with a size approximately double the minimum dimension of vias in the wafer and decrement in size to a size approximately half the minimum dimension.

摘要翻译： 在半导体制造工艺中预测通孔的蚀刻效能的方法，其中使用光焦点曝光矩阵（FEM）阵列作为通孔蚀刻监视器。 FEM是矩阵阵列，其中每个阵列具有不同大小的通孔集合。 阵列中的矩阵的大小大约是晶片中通孔的最小尺寸的两倍，尺寸减小到最小尺寸的一半左右。

公开(公告)号：US6154711A

公开(公告)日：2000-11-28

申请号：US985467

申请日：1997-12-05

申请人： Paul J. Steffan ,  Ming Chun Chen

发明人： Paul J. Steffan ,  Ming Chun Chen

IPC分类号： G03F7/20 ,  H01L21/66

CPC分类号： G03F7/70625 ,  H01L22/20

摘要： A method of manufacturing semiconductor wafers using a simulation tool to determine a set of predicted wafer electrical test parameters. The set of predicted wafer electrical test parameters are compared with wafer electrical test specifications tabulated for each process during the manufacturing process. During the comparison, it is determined whether the predicted wafer electrical test parameters are within the specifications for the process and circuit simulations are then conducted using the predicted wafer electrical test parameters. Device performance is predicted from the circuit simulations and the disposition of the wafer lot is determined utilizing tabulated from a disposition performance table.

摘要翻译： 使用模拟工具制造半导体晶片以确定一组预测的晶片电测试参数的方法。 将预测的晶片电气测试参数的集合与在制造过程期间针对每个处理列出的晶片电气测试规格进行比较。 在比较期间，确定预测的晶片电气测试参数是否在该处理的规格内，然后使用预测的晶片电气测试参数进行电路仿真。 根据电路模拟预测器件性能，并利用从配置性能表格列出来确定晶片批次的布置。

公开(公告)号：US6063685A

公开(公告)日：2000-05-16

申请号：US131284

申请日：1998-08-07

申请人： Paul J. Steffan ,  Michael McIntyre ,  Charlie Reading

发明人： Paul J. Steffan ,  Michael McIntyre ,  Charlie Reading

IPC分类号： H01L23/544 ,  H01L21/76

CPC分类号： H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2924/0002

摘要： A method of identifying individual semiconductor devices with a unique inscription during the manufacturing process for the semiconductor devices. Each individual semiconductor device is marked during a final lithographic stepping exposure with a direct write laser mounted either in the stepper in the lithographic system working concurrently with the stepping fields during the final metal layer lithographic stepping exposure or during a post stepping pre-development treatment. The marking on the devices includes device identification, lot number and die number.

摘要翻译： 一种在半导体器件的制造过程中识别具有独特铭文的各个半导体器件的方法。 每个单独的半导体器件在最终光刻步进曝光期间被标记，其中直接写入激光器安装在光刻系统中的步进器中，与最终金属层光刻步进曝光期间或在后期步进预处理中的步进场同时工作。 设备上的标记包括设备识别，批号和裸号。

公开(公告)号：US5985753A

公开(公告)日：1999-11-16

申请号：US136866

申请日：1998-08-19

申请人： Allen S. Yu ,  Paul J. Steffan ,  Thomas C. Scholer

发明人： Allen S. Yu ,  Paul J. Steffan ,  Thomas C. Scholer

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76825 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76813 ,  H01L2221/1026

摘要： Methods of manufacturing semiconductor devices wherein a selected layer is implanted with heavy ions in a pattern having dimensions of a via structure to be formed in a first layer of interlayer dielectric. In a first embodiment, the ions are implanted in an etch stop layer formed between a first and second layer of interlayer dielectric. In a second embodiment, the ions are implanted in the second layer of interlayer dielectric. Selective etch processes form a trench structure in the second layer of interlayer dielectric and form a via structure in the first layer of interlayer dielectric. The via structure and trench structure are filled with a conductive material.

摘要翻译： 制造半导体器件的方法，其中所选择的层以具有要形成在第一层间电介质层中的通孔结构的尺寸的图案中注入重离子。 在第一实施例中，将离子注入形成在第一和第二层间电介质层之间的蚀刻停止层中。 在第二实施例中，将离子注入第二层间电介质层。 选择性蚀刻工艺在第二层间电介质层中形成沟槽结构，并在第一层间电介质层中形成通孔结构。 通孔结构和沟槽结构填充有导电材料。

公开(公告)号：US5966459A

公开(公告)日：1999-10-12

申请号：US896341

申请日：1997-07-17

申请人： Ming Chun Chen ,  Paul J. Steffan

发明人： Ming Chun Chen ,  Paul J. Steffan

IPC分类号： G06T7/00 ,  G06K9/00

CPC分类号： G06K9/00 ,  G06T7/0002 ,  G06T7/0004 ,  G06K2209/19 ,  G06T2207/30148

摘要： A method of determining classification codes for defects occurring in semiconductor manufacturing processes and for storing the information used to determine the classification codes. A wafer is selected from a production lot after the lot is sent through a first manufacturing process. The selected wafer is scanned to determine if there are defects on the wafer. Images of selected defects are examined and a numerical value is assigned to each of N elemental descriptor terms describing each defect. A classification code is determined for each defect based upon the numerical values assigned to the N elemental descriptor terms. The classification code and numerical values assigned to the N elemental descriptor terms are stored in a database. The wafer is sent through each sequential process and classification codes are assigned to additional defects selected after each sequential process. The classification codes and numerical values assigned to the N elemental descriptor terms for the additional selected defects are stored in the database. The stored numerical values assigned to the N elemental descriptor terms to modify the classification code. All of the defects stored in the database are assigned new classification codes in accordance with the modified classification code. A new classification code can be generated and all of the stored defects are assigned new classification codes in accordance with the new database.

摘要翻译： 确定半导体制造过程中出现的缺陷的分类代码并存储用于确定分类代码的信息的方法。 在批次通过第一制造过程发送之后，从生产批次中选择晶片。 扫描所选择的晶片以确定晶片上是否存在缺陷。 检查所选缺陷的图像，并且将数值分配给描述每个缺陷的N个元素描述符术语中的每一个。 基于分配给N个元素描述符项的数值，为每个缺陷确定分类代码。 分配给N个元素描述符词的分类代码和数值被存储在数据库中。 通过每个顺序过程发送晶片，并且将分类代码分配给在每个顺序处理之后选择的附加缺陷。 分配给附加选定缺陷的N个元素描述符项的分类代码和数值存储在数据库中。 分配给N个元素描述符术语的存储数值修改分类代码。 存储在数据库中的所有缺陷都按照修改的分类代码分配新的分类代码。 可以生成新的分类代码，并根据新数据库为所有存储的缺陷分配新的分类代码。

公开(公告)号：US06424881B1

公开(公告)日：2002-07-23

申请号：US09404081

申请日：1999-09-23

申请人： Paul J. Steffan ,  Allen S. Yu

发明人： Paul J. Steffan ,  Allen S. Yu

IPC分类号： G06F1900

CPC分类号： H01L22/20

摘要： A method of manufacturing semiconductor devices wherein a computer generated list of appropriate review recipes for each layer is available to be used by a review station to review defects on each layer. The most appropriate review recipe is used by the review station unless a review station operator selects an alternate review recipe.

摘要翻译： 一种制造半导体器件的方法，其中计算机产生的每个层的适当的审查配方的列表可被审查站用于审查每个层上的缺陷。 审查站使用最合适的审查方法，除非审查站操作员选择备用审查配方。

公开(公告)号：US06421574B1

公开(公告)日：2002-07-16

申请号：US09404079

申请日：1999-09-23

申请人： Paul J. Steffan ,  Allen S. Yu

发明人： Paul J. Steffan ,  Allen S. Yu

IPC分类号： G06F1900

CPC分类号： H01L22/20

摘要： A method of manufacturing semiconductor devices in which scan data for a current layer of a wafer of a lot being manufactured is compared to previous scan data for previous lots that has been stored in a defect management system. The automatic defect classification system determines whether additional wafers need to be scanned in order to obtain accurate defect data for the production lot to determine whether the current lot should or should not be placed on hold.

摘要翻译： 一种制造半导体器件的方法，其中将要制造的批次的晶片的当前层的扫描数据与已经存储在缺陷管理系统中的先前批次的先前扫描数据进行比较。 自动缺陷分类系统确定是否需要扫描附加晶片，以获得生产批次的准确缺陷数据，以确定当前批次是否应该被搁置。