-
公开(公告)号:US06552839B1
公开(公告)日:2003-04-22
申请号:US10104692
申请日:2002-03-21
申请人: Yoon Shik Hong , Joon Seok Kang , Sang Kee Yoon , Sung Cheon Jung , Jung Hyun Lee , Hyun Kee Lee
发明人: Yoon Shik Hong , Joon Seok Kang , Sang Kee Yoon , Sung Cheon Jung , Jung Hyun Lee , Hyun Kee Lee
IPC分类号: G02B2600
CPC分类号: G02B6/358 , B81B3/0054 , B81B2201/045 , B81B2203/053 , G02B6/3514 , G02B6/3546 , G02B6/357 , G02B6/3584 , G02B26/0841 , H02N1/006
摘要: Disclosed herein is an optical switch. The optical switch includes an electrostatic actuator and a substrate. The electrostatic actuator includes an electrostatic actuator, the electrostatic actuator comprising, a reciprocating mass located in the center of the electrostatic actuator, first rotating axes located symmetrically at the left and right sides of the reciprocating mass, first rotating masses rotatably connected to the first rotating axes, first rotating springs for supporting the first rotating masses, linear springs connected to the first rotating masses, second rotating masses connected to the linear springs, second rotating springs for supporting the second rotating masses, second rotating axes connected to the second rotating masses, structural anchors at the side ends of the actuator, drive electrodes, and a micro mirror movable by the same displacement as the reciprocating mass.
摘要翻译: 这里公开了一种光开关。 光开关包括静电致动器和基板。 所述静电致动器包括静电致动器,所述静电致动器包括位于所述静电致动器的中心的往复运动物质,位于所述往复运动质量块的左右两侧的第一旋转轴,所述第一旋转体可旋转地连接到所述第一旋转 轴,用于支撑第一旋转块的第一旋转弹簧,连接到第一旋转块的线性弹簧,连接到线性弹簧的第二旋转块,用于支撑第二旋转块的第二旋转弹簧,连接到第二旋转块的第二旋转轴, 在致动器的侧端处的结构锚固件,驱动电极和可与往复运动块相同位移的微反射镜。
-
公开(公告)号:US06833288B2
公开(公告)日:2004-12-21
申请号:US10412465
申请日:2003-04-11
申请人: Joon Seok Kang , Sung Cheon Jung , Sang Kee Yoon , Hyun Kee Lee
发明人: Joon Seok Kang , Sung Cheon Jung , Sang Kee Yoon , Hyun Kee Lee
IPC分类号: H01L2144
CPC分类号: B81C1/00888 , B81C1/00896 , B81C2201/053
摘要: A dicing method for a micro electro mechanical system chip, in which a high yield and productivity of chips can be accomplished, resulting from preventing damage to microstructures during a dicing process by using a protective mask. The dicing method for a micro electro mechanical system chip, comprising the steps of designing a grid line and wafer pattern on a chip-scale on the non-adhesive surface of a transparent tape as a protective mask (first step); sticking microstructure-protecting membranes on the adhesive surface of the transparent tape (second step); putting the transparent tape on the whole surface of a wafer in a state wherein the grid line designed on the non-adhesive surface of the transparent tape is matched to the dicing line of the wafer (third step); cutting the transparent tape to a size larger than the wafer, mounting the wafer on a guide ring and dicing the wafer (fourth step); and separating the transparent tape from diced chips (fifth step).
摘要翻译: 一种用于微机电系统芯片的切割方法,其中可以通过使用保护掩模在切割过程中防止对微结构的损害而实现高产量和高生产率的芯片。 一种微机电系统芯片的切割方法,其特征在于,包括如下步骤:在作为保护罩的透明胶带的非粘合表面上以芯片尺度设计网格线和晶片图案(第一步骤)。 在透明胶带的粘合剂表面上粘附微结构保护膜(第二步); 将透明带放置在晶片的整个表面上,其中设计在透明带的非粘合表面上的栅格线与晶片的切割线相匹配(第三步)。 将透明胶带切割成比晶片大的尺寸,将晶片安装在引导环上并切割晶片(第四步骤); 并将透明胶带分离成切片(第五步)。
-
公开(公告)号:US08893380B2
公开(公告)日:2014-11-25
申请号:US12320492
申请日:2009-01-27
申请人: Hong Won Kim , Sung Yi , Tae Sung Jeong , Joon Seok Kang
发明人: Hong Won Kim , Sung Yi , Tae Sung Jeong , Joon Seok Kang
IPC分类号: H05K3/30 , H01L23/00 , H05K1/18 , H01L21/683 , H05K3/42
CPC分类号: H05K1/185 , H01L21/568 , H01L21/6835 , H01L24/18 , H01L24/19 , H01L24/82 , H01L24/96 , H01L2224/04105 , H01L2224/18 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01078 , H05K3/426 , H05K2201/10515 , H05K2201/10674 , H05K2203/1461 , Y10T29/4913 , Y10T29/49146 , Y10T29/49165
摘要: The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof and provides a chip embedded printed circuit board including: an insulating layer having vias formed therethrough; a first chip and a second chip embedded in the insulating layer and having pads, which are respectively exposed to upper and lower surfaces of the insulating layer, on one surfaces thereof; an upper pattern formed on the upper surface of the insulating layer to be connected to the pads of the first chip and the vias; and a lower pattern formed on the lower surface of the insulating layer to be connected to the pads of the second chip and the vias. Also, the present invention provides a manufacturing method of a chip embedded printed circuit board.
摘要翻译: 芯片嵌入式印刷电路板及其制造方法技术领域本发明涉及一种芯片嵌入式印刷电路板及其制造方法,其特征在于,提供一种芯片嵌入式印刷电路基板, 嵌入绝缘层中的第一芯片和第二芯片,并且在其一个表面上分别暴露于绝缘层的上表面和下表面的焊盘; 形成在绝缘层的上表面上以连接到第一芯片的焊盘和通孔的上部图案; 以及形成在绝缘层的下表面上以连接到第二芯片的焊盘和通孔的下图案。 另外,本发明提供一种嵌入式芯片的印刷电路板的制造方法。
-
公开(公告)号:US20130139753A1
公开(公告)日:2013-06-06
申请号:US13409791
申请日:2012-03-01
申请人: Joon Seok Kang , Seung Wan Shin
发明人: Joon Seok Kang , Seung Wan Shin
IPC分类号: C23C16/458 , C23C16/50
CPC分类号: H01J37/32091 , H01L21/68742
摘要: Disclosed herein is an apparatus for manufacturing a substrate. The apparatus for manufacturing a substrate includes: a reaction gas ejector ejecting reaction gas; a lift pin supporting the substrate and having a header contacting a rear surface of the substrate; and a support chuck having a lift pin insertion unit inserted with the lift pin and moving vertically and including a ring in a header insertion portion into which the header is inserted in the lift pin insertion unit.
摘要翻译: 本文公开了一种用于制造基板的装置。 用于制造衬底的装置包括:反应气体喷射器喷射反应气体; 支撑所述基板并且具有与所述基板的后表面接触的头部的升降销; 以及支撑卡盘,其具有插入所述提升销并垂直移动的升降销插入单元,并且在所述插头插入部中包括环,所述插头插入所述插头插入单元中。
-
公开(公告)号:US20110097856A1
公开(公告)日:2011-04-28
申请号:US12632611
申请日:2009-12-07
申请人: Hong Won KIM , Joon Seok Kang , Doo Sung Jung , Seon Hee Moon
发明人: Hong Won KIM , Joon Seok Kang , Doo Sung Jung , Seon Hee Moon
IPC分类号: H01L21/56
CPC分类号: H01L23/562 , H01L21/568 , H01L23/3171 , H01L24/19 , H01L24/96 , H01L2224/04105 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2924/00
摘要: Disclosed is a method of manufacturing a wafer level package, which includes arranging semiconductor dies on a carrier, forming a protective layer between the semiconductor dies of the carrier through screen printing, primarily heat hardening the protective layer, simultaneously pressing and secondarily heat hardening the protective layer, and removing the carrier, so that a thickness difference between the semiconductor dies and the protective layer is not formed and the warping of the wafer level package is reduced.
摘要翻译: 公开了一种制造晶片级封装的方法,其包括在载体上布置半导体管芯,通过丝网印刷在载体的半导体管芯之间形成保护层,主要将保护层加热硬化,同时加压硬化保护层 层,并且移除载体,使得半导体管芯和保护层之间的厚度差不会形成,并且晶片级封装的翘曲减小。
-
公开(公告)号:USD629023S1
公开(公告)日:2010-12-14
申请号:US29351778
申请日:2009-12-11
申请人: Sang Woon Jeon , Sei Ill Jeon , Joon Seok Kang , Jae Moon Lee
设计人: Sang Woon Jeon , Sei Ill Jeon , Joon Seok Kang , Jae Moon Lee
-
公开(公告)号:US20130319734A1
公开(公告)日:2013-12-05
申请号:US13595900
申请日:2012-08-27
申请人: Sang Hyun Shin , Kwang Jik Lee , Hye Sook Shin , Joon Seok Kang
发明人: Sang Hyun Shin , Kwang Jik Lee , Hye Sook Shin , Joon Seok Kang
CPC分类号: H01L21/486 , H01L23/142 , H01L23/49827 , H01L2924/0002 , H05K3/424 , H05K3/427 , H05K3/445 , H05K2201/0959 , H05K2203/0716 , H05K2203/1423 , H01L2924/00
摘要: Disclosed herein is a package substrate including: a base substrate; insulation layers formed on upper and lower portions of the base substrate; a first metal layer formed on an upper portion of the insulation layer; a first through-via penetrating through the base substrate, the insulation layer, and the first metal layer and being made of an insulating material; a seed layer formed on upper and lower portions and an inner wall of the first through-via; a second metal layer formed on upper portions of the first metal layer and the seed layer; and a second through-via formed in the seed layer formed at the inner wall of the first through-via and the second metal layer.
摘要翻译: 本文公开了一种封装衬底,包括:基底; 形成在基底基板的上部和下部的绝缘层; 形成在所述绝缘层的上部的第一金属层; 穿过基底基板,绝缘层和第一金属层并由绝缘材料制成的第一通孔; 形成在第一通孔的上部和下部以及内壁上的种子层; 形成在第一金属层和种子层的上部的第二金属层; 以及形成在形成在第一通孔和第二金属层的内壁处的种子层中的第二通孔。
-
18.
公开(公告)号:US20100142170A1
公开(公告)日:2010-06-10
申请号:US12320492
申请日:2009-01-27
申请人: Hong Won Kim , Sung Yi , Tae Sung Jeong , Joon Seok Kang
发明人: Hong Won Kim , Sung Yi , Tae Sung Jeong , Joon Seok Kang
CPC分类号: H05K1/185 , H01L21/568 , H01L21/6835 , H01L24/18 , H01L24/19 , H01L24/82 , H01L24/96 , H01L2224/04105 , H01L2224/18 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01078 , H05K3/426 , H05K2201/10515 , H05K2201/10674 , H05K2203/1461 , Y10T29/4913 , Y10T29/49146 , Y10T29/49165
摘要: The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof and provides a chip embedded printed circuit board including: an insulating layer having vias formed therethrough; a first chip and a second chip embedded in the insulating layer and having pads, which are respectively exposed to upper and lower surfaces of the insulating layer, on one surfaces thereof; an upper pattern formed on the upper surface of the insulating layer to be connected to the pads of the first chip and the vias; and a lower pattern formed on the lower surface of the insulating layer to be connected to the pads of the second chip and the vias. Also, the present invention provides a manufacturing method of a chip embedded printed circuit board.
摘要翻译: 芯片嵌入式印刷电路板及其制造方法技术领域本发明涉及一种芯片嵌入式印刷电路板及其制造方法,其特征在于,提供一种芯片嵌入式印刷电路板,其具备:具有通孔形成的绝缘层; 嵌入绝缘层中的第一芯片和第二芯片,并且在其一个表面上分别暴露于绝缘层的上表面和下表面的焊盘; 形成在绝缘层的上表面上以连接到第一芯片的焊盘和通孔的上部图案; 以及形成在绝缘层的下表面上以连接到第二芯片的焊盘和通孔的下图案。 另外,本发明提供一种嵌入式芯片的印刷电路板的制造方法。
-
19.
公开(公告)号:US20100134991A1
公开(公告)日:2010-06-03
申请号:US12320523
申请日:2009-01-28
申请人: Hong Won Kim , Sung Yi , Tae Sung Jeong , Joon Seok Kang
发明人: Hong Won Kim , Sung Yi , Tae Sung Jeong , Joon Seok Kang
CPC分类号: H05K1/185 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/82039 , H01L2224/82047 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H05K2201/0355 , H05K2201/0394 , H05K2201/10674 , H05K2203/1469 , Y10T29/49128 , Y10T29/4913 , Y10T29/49146 , Y10T29/49147 , Y10T29/49155
摘要: The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof. The prevent invention provides the chip embedded printed circuit board including an insulating layer embedding a chip provided with posts at an upper part, vias formed through the insulating layer, upper patterns formed at the upper part of the insulating layer to be connected to the posts and the vias and lower patterns formed at a lower part of the insulating layer to be connected to the vias, and the manufacturing method thereof.
摘要翻译: 芯片嵌入式印刷电路板及其制造方法技术领域本发明涉及一种嵌入式芯片的印刷电路板及其制造方法。 本发明提供了一种芯片嵌入式印刷电路板,其包括:绝缘层,其嵌入在上部设置有柱的芯片,通过绝缘层形成的通孔,形成在要连接到柱的绝缘层的上部的上部图案;以及 形成在绝缘层的与通孔连接的下部的通孔和下部图案及其制造方法。
-
-
-
-
-
-
-
-