公开(公告)号：US20120139047A1

公开(公告)日：2012-06-07

申请号：US13380096

申请日：2011-02-27

Applicant: Jun Luo ,  Chao Zhao

Inventor： Jun Luo ,  Chao Zhao

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/47 ,  H01L29/66643 ,  H01L29/66772 ,  H01L29/7839

Abstract: Disclosed is a semiconductor device, comprising a substrate, a channel region in the substrate, source/drain regions on both sides of the channel region, a gate structure on the channel region, and gate sidewall spacers formed on the sidewalls of the gate structure, characterized in that each of the source/drain regions comprises an epitaxially grown metal silicide region, and dopant segregation regions are formed at the interfaces between the epitaxially grown metal silicide source/drain regions and the channel region. By employing the semiconductor device and the method for manufacturing the same according to embodiments of the present invention, the Schottkey Barrier Height of the MOSFETs with epitaxially grown ultrathin metal silicide source/drain may be lowered, thereby improving the driving capability.

Abstract translation: 公开了一种半导体器件，包括衬底，衬底中的沟道区域，沟道区两侧的源极/漏极区域，沟道区域上的栅极结构以及形成在栅极结构的侧壁上的栅极侧壁间隔物， 其特征在于，每个源极/漏极区域包括外延生长的金属硅化物区域，并且在外延生长的金属硅化物源极/漏极区域和沟道区域之间的界面处形成掺杂剂偏析区域。 通过采用根据本发明的实施例的半导体器件及其制造方法，可以降低具有外延生长的超薄金属硅化物源极/漏极的MOSFET的肖特基势垒高度，从而提高驱动能力。

公开(公告)号：US09012965B2

公开(公告)日：2015-04-21

申请号：US13379120

申请日：2011-04-22

Applicant: Jun Luo ,  Chao Zhao

Inventor： Jun Luo ,  Chao Zhao

IPC: H01L29/76 ,  H01L29/47 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/265

CPC classification number: H01L29/47 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/66545 ,  H01L29/66643 ,  H01L29/7839

Abstract: The invention discloses a novel MOSFET device fabricated by a gate last process and its implementation method, the device comprising: a substrate; a gate stack structure located on a channel region in the substrate, on either side of which is eliminated the conventional isolation spacer; an epitaxially grown ultrathin metal silicide constituting a source/drain region. Wherein the device eliminates the high resistance region below the conventional isolation spacer; a dopant segregation region with imlanted ions is formed between the source/drain and the channel region, which decreases the Schottky barrier height between the metal silicide source/drain and the channel. At the same time, the epitaxially grown metal silicide can withstand a second high-temperature annealing used for improving the performance of a high-k gate dielectric material, which further improves the performance of the device. The MOSFET according to the invention reduces the parasitic resistance and capacitance greatly and thereby decreases the RC delay, thus improving the switching performance of the MOSFET device significantly.

Abstract translation: 本发明公开了一种通过门最后工艺制造的新型MOSFET器件及其实现方法，该器件包括：衬底; 栅极叠层结构位于衬底的沟道区上，其任一侧消除了传统隔离间隔物; 构成源极/漏极区域的外延生长的超薄金属硅化物。 其中该器件消除了传统隔离间隔物下面的高电阻区域; 在源极/漏极和沟道区之间形成具有经过离子注入的掺杂剂偏析区域，这降低了金属硅化物源极/漏极与沟道之间的肖特基势垒高度。 同时，外延生长的金属硅化物可以承受用于改善高k栅介质材料性能的第二高温退火，这进一步提高了器件的性能。 根据本发明的MOSFET大大降低了寄生电阻和电容，从而降低了RC延迟，从而显着提高了MOSFET器件的开关性能。

公开(公告)号：US20140302644A1

公开(公告)日：2014-10-09

申请号：US14361944

申请日：2012-03-23

Applicant: Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

Inventor： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

IPC: H01L21/28 ,  H01L21/283 ,  H01L29/66

CPC classification number: H01L21/28097 ,  H01L21/283 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate. The method for manufacturing the semiconductor device according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH between the Nickel-based metal silicide and the silicon channel is effectively reduced, and the driving capability of the device is improved.

Abstract translation: 本发明公开了一种制造半导体器件的方法，包括：在硅衬底上形成栅层叠结构; 在基板上沉积镍基金属层和栅极堆叠结构; 进行第一退火，使得衬底中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使得金属与硅化物的富Ni相转变为镍基金属硅化物源极/漏极，同时在镍基金属硅化物源之间的界面处形成掺杂离子的偏析区域 /漏极和衬底。 根据本发明的制造半导体器件的方法在将掺杂离子注入到金属硅化物的富Ni相中之后进行退火，从而提高掺杂离子的固溶度并形成高浓度掺杂离子的偏析区域， 因此有效地降低了镍基金属硅化物与硅通道之间的SBH，提高了器件的驱动能力。

公开(公告)号：US08816326B2

公开(公告)日：2014-08-26

申请号：US13497249

申请日：2011-11-25

Applicant: Huaxiang Yin ,  Jun Luo ,  Chao Zhao ,  Honggang Liu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Jun Luo ,  Chao Zhao ,  Honggang Liu ,  Dapeng Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/778 ,  H01L29/08

CPC classification number: H01L29/66462 ,  H01L29/0895 ,  H01L29/7391 ,  H01L29/7785 ,  Y10S977/938

Abstract: A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.

Abstract translation: 一种半导体器件，包括：半导体衬底; 半导体衬底上的沟道区，所述沟道区包括量子阱结构; 在沟道区域的侧面上的源极区域和漏极区域; 通道区域上的栅极结构; 其中用于沟道区，源区和漏区的材料具有不同的能带，并且在源极区域和沟道区域之间存在隧道势垒结构。

公开(公告)号：US08536053B2

公开(公告)日：2013-09-17

申请号：US13063922

申请日：2011-01-27

Applicant: Jun Luo ,  Chao Zhao ,  Huicai Zhong

Inventor： Jun Luo ,  Chao Zhao ,  Huicai Zhong

IPC: H01L21/28

CPC classification number: H01L29/41775 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method for restricting lateral encroachment of the metal silicide into the channel region, comprising: providing a semiconductor substrate, a gate stack being formed on the semiconductor substrate, a source region being formed in the semiconductor on one side of the gate stack, and a drain region being formed in the semiconductor substrate on the other side of the gate stack; forming a sacrificial spacer around the gate stack and on the semiconductor substrate; depositing a metal layer for covering the semiconductor substrate, the gate stack and the sacrificial spacer; performing a thermal treatment on the semiconductor substrate, thereby causing the metal layer to react with the sacrificial spacer and the semiconductor substrate in the source region and the drain region; removing the sacrificial spacer, reaction products of the sacrificial spacer and the metal layer, and a part of the metal layer which does not react with the sacrificial spacer.

Abstract translation: 一种用于限制金属硅化物向通道区域的横向侵入的方法，包括：提供半导体衬底，形成在半导体衬底上的栅堆叠，形成在栅叠层一侧的半导体中的源区， 漏极区域形成在栅极堆叠的另一侧上的半导体衬底中; 在所述栅极堆叠和所述半导体衬底上形成牺牲隔离物; 沉积用于覆盖半导体衬底，栅极堆叠和牺牲间隔物的金属层; 对所述半导体基板进行热处理，由此使所述金属层与所述源极区域和所述漏极区域中的所述牺牲隔离物和所述半导体基板反应; 去除牺牲间隔物，牺牲间隔物和金属层的反应产物，以及不与牺牲间隔物反应的金属层的一部分。

公开(公告)号：US20130221414A1

公开(公告)日：2013-08-29

申请号：US13697319

申请日：2012-03-26

Applicant: Chao Zhao ,  Jun Luo ,  Huicai Zhong

Inventor： Chao Zhao ,  Jun Luo ,  Huicai Zhong

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: The present invention provides a semiconductor FET and a method for manufacturing the same. The semiconductor FET may comprise: a gate wall; a fin outside the gate wall, both ends of the fin being connected with the source/drain regions on both ends of the fin; and a contact wall on both sides of the gate wall, the contact wall being connected with the source/drain regions via the underlying silicide layer, wherein an airgap is provided around the gate wall. Since an airgap is formed around the gate wall, and particularly the airgap is formed between the gate wall and the contact wall, it is possible to decrease the parasitic capacitance between the gate wall and the contact wall. As a result, the problem of excessive parasitic capacitance resulting from use of the contact wall can be effectively alleviated.

Abstract translation: 本发明提供一种半导体FET及其制造方法。 半导体FET可以包括：栅极壁; 在门壁外的翅片，翅片的两端与翅片两端的源极/漏极区域连接; 以及在栅极壁的两侧上的接触壁，所述接触壁经由下面的硅化物层与源极/漏极区域连接，其中在栅极壁周围设置气隙。 由于在栅极壁周围形成气隙，特别是在栅极壁和接触壁之间形成气隙，因此能够降低栅极壁与接触壁之间的寄生电容。 结果，可以有效地缓解由使用接触壁引起的过大的寄生电容的问题。

公开(公告)号：US20130062708A1

公开(公告)日：2013-03-14

申请号：US13577942

申请日：2011-11-18

Applicant: Huicai Zhong ,  Qingqing Liang ,  Jun Luo ,  Chao Zhao

Inventor： Huicai Zhong ,  Qingqing Liang ,  Jun Luo ,  Chao Zhao

IPC: H01L21/762 ,  H01L27/088

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices.

Abstract translation: 公开了一种半导体器件结构，其制造方法和半导体鳍片的制造方法。 在一个实施例中，制造半导体器件结构的方法包括：在半导体衬底上沿第一方向形成翅片; 在第二方向上形成栅极线，在半导体衬底上与第一方向交叉的第二方向和与鳍状物交叉的栅极线与夹在栅极线和鳍之间的栅极电介质层形成栅极线; 形成围绕所述栅极线的介电隔离层; 以及在预定位置执行器件间电隔离，其中所述栅极线的隔离部分形成各个器件的独立栅电极。

公开(公告)号：US09224589B2

公开(公告)日：2015-12-29

申请号：US13497768

申请日：2011-11-28

Applicant: Guilei Wang ,  Junfeng Li ,  Chao Zhao

Inventor： Guilei Wang ,  Junfeng Li ,  Chao Zhao

IPC: H01L21/02 ,  H01L21/768 ,  C23C16/44 ,  C23C16/30 ,  C23C16/34 ,  C23C16/40 ,  C23C16/505 ,  C23C16/56

CPC classification number: H01L21/02 ,  C23C16/308 ,  C23C16/345 ,  C23C16/402 ,  C23C16/4404 ,  C23C16/505 ,  C23C16/56 ,  H01L21/76837

Abstract: A method for eliminating contact bridge in a contact hole process is disclosed, wherein a cleaning menu comprising a multi-step adaptive protective thin film deposition process is provided, so that a stack adaptive protective thin film is formed on the sidewall of the chamber of the HDP CVD equipment. The stack adaptive protective thin film has good adhesivity, compactness and uniformity to protect the sidewall of the chamber of the HDP CVD equipment from being damaged by the plasma, and avoid the generation of defect particles, thereby improving the HDP CVD technical yield and eliminating the contact bridge phenomenon in the contact hole process.

Abstract translation: 公开了一种用于消除接触孔工艺中的接触桥的方法，其中提供了包括多步自适应保护薄膜沉积工艺的清洁菜单，使得堆叠自适应保护薄膜形成在腔室的侧壁上 HDP CVD设备。 叠层自适应保护薄膜具有良好的粘合性，紧凑性和均匀性，以保护HDP CVD设备室的侧壁不被等离子体损坏，并避免产生缺陷颗粒，从而提高HDP CVD技术产量并消除 接触孔过程中的接触桥现象。

公开(公告)号：US20150035087A1

公开(公告)日：2015-02-05

申请号：US14119864

申请日：2012-12-12

Applicant: Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/518

Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.

Abstract translation: 提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成光致抗蚀剂线，并修整所形成的光致抗蚀剂线，使得修整的光致抗蚀剂线的宽度小于或等于22nm; 并根据修整的光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层无定形 硅。

公开(公告)号：US20140332958A1

公开(公告)日：2014-11-13

申请号：US14119862

申请日：2012-12-12

Applicant: Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L21/28123 ,  H01L29/4232 ,  H01L29/78

Abstract: A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer α-Si. Correspondingly, a dummy gate in a gate-last process is also provided.

Abstract translation: 提供了一种在门最后工艺中制造虚拟栅极的方法。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成宽度范围为32nm至45nm的光致抗蚀剂线; 根据光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层α- Si。 相应地，还提供了最后进程中的虚拟门。