公开(公告)号：US10685972B2

公开(公告)日：2020-06-16

申请号：US15514239

申请日：2014-09-26

申请人： Sunggil Kim ,  Phil Ouk Nam ,  Gukhyon Yon ,  Sunghae Lee ,  Woojin Jang ,  Dongchul Yoo ,  Hunhyeong Lim ,  Junggeun Jee ,  Kihyun Hwang

发明人： Sunggil Kim ,  Phil Ouk Nam ,  Gukhyon Yon ,  Sunghae Lee ,  Woojin Jang ,  Dongchul Yoo ,  Hunhyeong Lim ,  Junggeun Jee ,  Kihyun Hwang

IPC分类号： H01L27/11582 ,  H01L27/11568 ,  H01L21/28 ,  H01L27/115 ,  H01L49/02 ,  H01L21/02 ,  H01L21/311 ,  H01L27/1157 ,  H01L29/10

摘要： The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.

公开(公告)号：US08697498B2

公开(公告)日：2014-04-15

申请号：US13284435

申请日：2011-10-28

申请人： Byong-hyun Jang ,  Dongchul Yoo ,  Chanjin Park ,  Hanmei Choi

发明人： Byong-hyun Jang ,  Dongchul Yoo ,  Chanjin Park ,  Hanmei Choi

IPC分类号： H01L21/82 ,  H01L21/00

CPC分类号： H01L21/762 ,  H01L21/76224 ,  H01L27/1157 ,  H01L27/11582

摘要： A method of manufacturing a Three Dimensional (3D) semiconductor memory device can be provided by forming at least one trench in a plate stack structure to divide the plate stack structure into a plurality of sub-plate stack structures between forming a plurality of vertical active patterns in the plate stack structure and forming pads of a stepped structure from the plate stack structure.

摘要翻译： 可以通过在板堆叠结构中形成至少一个沟槽来形成制造三维（3D）半导体存储器件的方法，以在形成多个垂直有源图案之间将板堆叠结构分成多个子板堆叠结构 在板堆叠结构中和从板堆叠结构的阶梯结构的成形垫。

公开(公告)号：US09536970B2

公开(公告)日：2017-01-03

申请号：US13072078

申请日：2011-03-25

申请人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Dongchul Yoo ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

发明人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Dongchul Yoo ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC分类号： H01L29/792 ,  H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H01L27/115 ,  H01L29/51

CPC分类号： H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US09536897B2

公开(公告)日：2017-01-03

申请号：US14695249

申请日：2015-04-24

申请人： Dongchul Yoo ,  Chaeho Kim ,  Jaeyoung Ahn ,  Woong Lee

发明人： Dongchul Yoo ,  Chaeho Kim ,  Jaeyoung Ahn ,  Woong Lee

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole.

摘要翻译： 三维半导体器件可以包括包括单元阵列区域，字线接触区域和外围电路区域的基板，堆叠在基板上以从单元阵列区域延伸到字线接触区域的栅电极，通道 穿透单元阵列区域上的栅电极并暴露基板的有源区域，穿过字线接触区域上的栅电极的裸孔，并暴露设置在基板上的器件隔离层，以及设置在基极上的半导体图案 通道孔，但不在虚拟孔中。

公开(公告)号：US09515086B2

公开(公告)日：2016-12-06

申请号：US14834454

申请日：2015-08-25

申请人： Gukhyon Yon ,  Jaeyoung Ahn ,  Bio Kim ,  Young-Jin Noh ,  Kwangmin Park ,  Dongchul Yoo

发明人： Gukhyon Yon ,  Jaeyoung Ahn ,  Bio Kim ,  Young-Jin Noh ,  Kwangmin Park ,  Dongchul Yoo

IPC分类号： H01L27/115 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7926

摘要： Provided are a three dimensional semiconductor memory device and a method of fabricating the same. In the three dimensional semiconductor memory device, a stack of gate electrodes and insulating layers may be formed on a substrate, a channel structure may extend through the stack and connect to the substrate. A blocking insulating layer, a charge storing layer and a tunnel insulating layer may be formed between each gate electrode and the channel structure. The tunnel insulating layer may include a high-k dielectric layer with a low charge trap site density. The tunnel insulating layer may also include a first and a second tunnel insulating layers, and the high-k dielectric layer is provided between the first and second tunnel insulating layers.

摘要翻译： 提供三维半导体存储器件及其制造方法。 在三维半导体存储器件中，可以在衬底上形成一叠栅极电极和绝缘层，沟道结构可以延伸通过堆叠并连接至衬底。 可以在每个栅电极和沟道结构之间形成阻挡绝缘层，电荷存储层和隧道绝缘层。 隧道绝缘层可以包括具有低电荷陷阱位点密度的高k电介质层。 隧道绝缘层还可以包括第一和第二隧道绝缘层，并且高k电介质层设置在第一和第二隧道绝缘层之间。

公开(公告)号：US20120001345A1

公开(公告)日：2012-01-05

申请号：US13173304

申请日：2011-06-30

申请人： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

发明人： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

IPC分类号： H01L23/48 ,  H01L21/306 ,  H01L21/768

CPC分类号： H01L29/788 ,  H01L23/5384 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

摘要翻译： 提供三维半导体器件。 该装置可以包括垂直和顺序堆叠的模具层，堆叠的模具层之间的导电图案，垂直穿过堆叠的模具层的插入图案，导电图案和插入图案之间的中间图案，以及模具层之间的保护层图案 和封堵图案，其中保护层图案由中间图案分离。