公开(公告)号：US20160293765A1

公开(公告)日：2016-10-06

申请号：US15182343

申请日：2016-06-14

申请人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

发明人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/51 ,  H01L29/04 ,  H01L29/66

CPC分类号： H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

公开(公告)号：US20140035009A1

公开(公告)日：2014-02-06

申请号：US14048923

申请日：2013-10-08

申请人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

发明人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC分类号： H01L29/04

CPC分类号： H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

摘要翻译： 对半导体膜的图案化方法进行说明。 根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密 并且其中所述硬掩模形成在所述第二晶体平面上。 接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。 然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

公开(公告)号：US07279375B2

公开(公告)日：2007-10-09

申请号：US11173866

申请日：2005-06-30

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark L. Doczy ,  Justin K. Brask ,  Uday Shah ,  Suman Datta ,  Robert S. Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark L. Doczy ,  Justin K. Brask ,  Uday Shah ,  Suman Datta ,  Robert S. Chau

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78684 ,  H01L2029/7858

摘要： A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

公开(公告)号：US20150102429A1

公开(公告)日：2015-04-16

申请号：US14576111

申请日：2014-12-18

申请人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

发明人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC分类号： H01L29/04 ,  H01L21/308 ,  H01L29/78

CPC分类号： H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

公开(公告)号：US08581258B2

公开(公告)日：2013-11-12

申请号：US13277897

申请日：2011-10-20

申请人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

发明人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC分类号： H01L21/00

CPC分类号： H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

公开(公告)号：US20090218603A1

公开(公告)日：2009-09-03

申请号：US12463309

申请日：2009-05-08

申请人： Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau ,  Brian S. Doyle

发明人： Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau ,  Brian S. Doyle

IPC分类号： H01L29/04

CPC分类号： H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

摘要翻译： 描述了半导体膜的图案化方法。 根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密 并且其中所述硬掩模形成在所述第二晶体平面上。 接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。 然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

公开(公告)号：US07326656B2

公开(公告)日：2008-02-05

申请号：US11362453

申请日：2006-02-24

申请人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

发明人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

IPC分类号： H01L21/31

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

公开(公告)号：US20130264642A1

公开(公告)日：2013-10-10

申请号：US13908858

申请日：2013-06-03

申请人： Uday Shah ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

发明人： Uday Shah ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

IPC分类号： H01L29/78

CPC分类号： H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 具有形成在基板的绝缘层上的半导体本体的非平面半导体器件。 半导体本体具有与形成在绝缘层上的底表面相对的顶表面和一对横向相对的侧壁，其中在顶表面处的横向相对侧壁之间的距离大于底表面处的距离。 栅电介质层形成在半导体本体的顶表面和半导体本体的侧壁上。 栅极电极形成在半导体本体的顶表面和侧壁上的栅介质层上。 在栅电极的相对侧的半导体本体中形成一对源极/漏极区域。

公开(公告)号：US20090090976A1

公开(公告)日：2009-04-09

申请号：US12333248

申请日：2008-12-11

申请人： Jack T. Kavalieros ,  Justin K. Brask ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Mark L. Doczy ,  Matthew V. Metz ,  Robert S. Chau

发明人： Jack T. Kavalieros ,  Justin K. Brask ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Mark L. Doczy ,  Matthew V. Metz ,  Robert S. Chau

IPC分类号： H01L29/78

CPC分类号： H01L21/823828 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.

摘要翻译： 一种能够将平面和非平面晶体管集成到体半导体衬底上的工艺，其中所有晶体管的沟道可在连续的宽度范围内定义。

公开(公告)号：US20140239358A1

公开(公告)日：2014-08-28

申请号：US14273373

申请日：2014-05-08

申请人： Uday Shah ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

发明人： Uday Shah ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

IPC分类号： H01L29/78

CPC分类号： H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 具有形成在基板的绝缘层上的半导体本体的非平面半导体器件。 半导体本体具有与形成在绝缘层上的底表面相对的顶表面和一对横向相对的侧壁，其中在顶表面处的横向相对侧壁之间的距离大于底表面处的距离。 栅电介质层形成在半导体本体的顶表面和半导体本体的侧壁上。 栅极电极形成在半导体本体的顶表面和侧壁上的栅介质层上。 在栅电极的相对侧的半导体本体中形成一对源极/漏极区域。