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11.发明授权Programmable event driven yield mechanism which may activate service threads 有权可编程事件驱动的产生机制，可以激活服务线程公开(公告)号：US07849465B2
公开(公告)日：2010-12-07
申请号：US11134687
申请日：2005-05-19
申请人： Xiang Zou , Hong Wang , Scott Dion Rodgers , Darrell D. Boggs , Bryant Bigbee , Shivanandan Kaushik , Anil Aggarwal , Ittai Anati , Doron Orenstein , Per Hammarlund , John Shen , Larry O. Smith , James B. Crossland , Chris J. Newburn
发明人： Xiang Zou , Hong Wang , Scott Dion Rodgers , Darrell D. Boggs , Bryant Bigbee , Shivanandan Kaushik , Anil Aggarwal , Ittai Anati , Doron Orenstein , Per Hammarlund , John Shen , Larry O. Smith , James B. Crossland , Chris J. Newburn
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3009 , G06F9/4843 , G06F11/3409 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.
摘要翻译： 用于可激活其他线程的可编程事件驱动产量机制的方法，装置和系统。 收益机制可以允许在出现体系结构定义的条件时触发可以执行当前与主线程的服务线程。 响应于条件，可以在操作系统的有限干预下激活服务线程。 在一个实施例中，装置包括执行多个指令的执行资源和监视器以检测体系结构定义的条件。 该装置可以包括事件处理程序，用于处理当检测到体系结构定义的条件时产生的产出事件。 可以使用包括处理器指令和通道寄存器在内的架构机制来允许用户级代码来实现产出事件机制。 还描述和要求保护其他实施例。
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公开(公告)号：US08984199B2
公开(公告)日：2015-03-17
申请号：US10631522
申请日：2003-07-31
CPC分类号： G06F9/4812 , G06F9/544
摘要： According to an embodiment of the invention, a method and apparatus for inter-processor interrupts in a multi-processor system are described. An embodiment comprises writing an inter-processor interrupt request to a first memory location; monitoring the first memory location; detecting the inter-processor interrupt request in the first memory location; calling a function for the inter-processor interrupt request; and performing the function for the inter-processor interrupt request.
摘要翻译： 根据本发明的实施例，描述了用于多处理器系统中的处理器间中断的方法和装置。 一个实施例包括将处理器间中断请求写入第一存储器位置; 监控第一个内存位置; 检测第一存储器位置中的处理器间中断请求; 调用处理器间中断请求的功能; 并执行处理器间中断请求的功能。
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公开(公告)号：US07328293B2
公开(公告)日：2008-02-05
申请号：US11716377
申请日：2007-03-09
CPC分类号： G06F9/526 , G06F1/3203 , G06F9/3004 , G06F9/30083 , G06F9/30087 , G06F9/3851
摘要： A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.
摘要翻译： 提供了一种使用监视器 - 内存等待监视锁定的方法，装置和系统。 根据一个实施例，监视与竞争锁相关联的节点; 并且寻求有争议的锁的处理器进入休眠状态直到发生监视事件。
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公开(公告)号：US07213093B2
公开(公告)日：2007-05-01
申请号：US10608708
申请日：2003-06-27
CPC分类号： G06F9/526 , G06F1/3203 , G06F9/3004 , G06F9/30083 , G06F9/30087 , G06F9/3851
摘要： A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.
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15.发明授权公开(公告)号：US09081707B2
公开(公告)日：2015-07-14
申请号：US13730906
申请日：2012-12-29
申请人： Shaun M. Conrad , Russell J. Fenger , Gaurav Khanna , Rahul Seth , James B. Crossland , Anil Aggarwal
发明人： Shaun M. Conrad , Russell J. Fenger , Gaurav Khanna , Rahul Seth , James B. Crossland , Anil Aggarwal
CPC分类号： G06F12/1027 , G06F1/3206 , G06F2212/683 , Y02D10/13
摘要： A method is described that includes recognizing that TLB information of one or more hardware threads is to be invalidated. The method also includes determining which ones of the one or more hardware threads are in a state in which TLB information is flushed. The method also includes directing a TLB shootdown to those of the or more hardware threads that are in a state in which TLB information is not flushed.
摘要翻译： 描述了包括识别一个或多个硬件线程的TLB信息被无效的方法。 该方法还包括确定一个或多个硬件线程中的哪一个处于其中刷新TLB信息的状态。 该方法还包括将TLB拍摄定向到处于未刷新TLB信息的状态的那些或更多个硬件线程。
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公开(公告)号：US07640384B2
公开(公告)日：2009-12-29
申请号：US11903249
申请日：2007-09-20
CPC分类号： G06F9/526 , G06F1/3203 , G06F9/3004 , G06F9/30083 , G06F9/30087 , G06F9/3851
摘要： A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. In one embodiment, a memory to store instructions to perform functions of a monitoring mechanism is provided. The monitoring mechanism having a first logic to cause a processor to exit a sleep state in response to an event, wherein exiting the sleep state comprises resuming control of processing resources that were relinquished by the processor during the sleep state. The monitoring mechanism having a second logic to disable monitoring of a node associated with a contended lock after the processor exits the sleep state.
摘要翻译： 提供了一种使用监视器 - 内存等待监视锁定的方法，装置和系统。 在一个实施例中，提供了存储用于执行监视机制的功能的指令的存储器。 监视机制具有使处理器响应于事件退出休眠状态的第一逻辑，其中退出休眠状态包括恢复处理在休眠状态期间被处理器放弃的处理资源的控制。 所述监视机制具有第二逻辑，以在所述处理器退出所述睡眠状态之后禁用与竞争锁相关联的节点的监视。
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公开(公告)号：US20140136746A1
公开(公告)日：2014-05-15
申请号：US13675868
申请日：2012-11-13
申请人： Keshavan Tiruvallur , Rajesh Parthasarathy , James B. Crossland , Shivnandan Kaushik , Luke Hood
发明人： Keshavan Tiruvallur , Rajesh Parthasarathy , James B. Crossland , Shivnandan Kaushik , Luke Hood
IPC分类号： G06F13/24
摘要： A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).
摘要翻译： 一种在计算机系统内实现高效中断通信的技术。 在一个实施例中，高级可编程中断控制器（APIC）通过使用各种接口指令或操作的APIC接口寄存器内的一组位而不使用存储器映射的输入/输出（MMIO）进行接口。
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公开(公告)号：US20130219154A1
公开(公告)日：2013-08-22
申请号：US13837923
申请日：2013-03-15
申请人： Don A. Van Dyke , Michael Mishaeli , Ittai Anati , Baiju V. Patel , Will Deutsch , Rajesh Shah , Gilbert Neiger , James B. Crossland , Chris J. Newburn , Bryant E. Bigbee , Muhammad Faisal Azeem , John L. Reid , Dion Rodgers
发明人： Don A. Van Dyke , Michael Mishaeli , Ittai Anati , Baiju V. Patel , Will Deutsch , Rajesh Shah , Gilbert Neiger , James B. Crossland , Chris J. Newburn , Bryant E. Bigbee , Muhammad Faisal Azeem , John L. Reid , Dion Rodgers
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30003 , G06F9/30101 , G06F9/461
摘要： Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.
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19.发明申请SYSTEM, APPARATUS, AND METHOD FOR SEGMENT REGISTER READ AND WRITE REGARDLESS OF PRIVILEGE LEVEL 有权系统，设备和分段注册读取和写入权限的优先权级别公开(公告)号：US20120166767A1
公开(公告)日：2012-06-28
申请号：US12976981
申请日：2010-12-22
IPC分类号： G06F9/312
CPC分类号： G06F9/30032 , G06F9/30101 , G06F9/342
摘要： Embodiments of systems, apparatuses, and methods for performing privilege agnostic segment base register read or write instruction are described. An exemplary method may include fetching the privilege agnostic segment base register write instruction, wherein the privilege agnostic write instruction includes a 64-bit data source operand, decoding the fetched privilege agnostic segment base register write instruction, and executing the decoded privilege agnostic segment base register write instruction to write the 64-bit data of the source operand into the segment base register identified by the opcode of the privilege agnostic segment base register write instruction.
摘要翻译： 描述用于执行特权不可知段段基址寄存器读或写指令的系统，装置和方法的实施例。 一种示例性方法可以包括获取特权不可知段基址寄存器写指令，其中特权不可知写指令包括64位数据源操作数，对获取的特权不可知段基址寄存器写指令进行解码，以及执行解码的特权不可知段基址寄存器 写指令将源操作数的64位数据写入由特权不可知段基址寄存器写指令的操作码标识的段基寄存器中。
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20.发明申请MANAGING AND IMPLEMENTING METADATA IN CENTRAL PROCESSING UNIT USING REGISTER EXTENSIONS 有权使用注册扩展管理和实施中央处理单元中的元数据公开(公告)号：US20110078389A1
公开(公告)日：2011-03-31
申请号：US12571269
申请日：2009-09-30
申请人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jocob Gottlieb
发明人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jocob Gottlieb
CPC分类号： G06F9/3013 , G06F9/30105 , G06F9/30112 , G06F9/32 , G06F9/342 , G06F9/35 , G06F12/1441
摘要： A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.
摘要翻译： 一组处理器的默认寄存器被扩展到计算机系统的处理器上的元数据寄存器。 存储有数据的默认寄存器，而与数据相关的元数据分别存储在元数据寄存器上。
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