公开(公告)号：USRE49152E1

公开(公告)日：2022-07-26

申请号：US16926273

申请日：2020-07-10

Applicant: Kioxia Corporation

Inventor： Ryota Katsumata ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC: G11C11/14 ,  H01L27/11578 ,  G11C16/04 ,  G11C16/06 ,  H01L27/11565 ,  H01L27/11582

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

公开(公告)号：US11374021B2

公开(公告)日：2022-06-28

申请号：US17141534

申请日：2021-01-05

Applicant: Kioxia Corporation

Inventor： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC: H01L27/11 ,  H01L27/11582 ,  H01L21/822 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11556 ,  G11C16/04

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

公开(公告)号：US20220173124A1

公开(公告)日：2022-06-02

申请号：US17672819

申请日：2022-02-16

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Shinya Arai ,  Masaki Tsuji ,  Hideaki Aochi ,  Hiroyasu Tanaka

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US11792992B2

公开(公告)日：2023-10-17

申请号：US17576164

申请日：2022-01-14

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC: H01L29/76 ,  H10B43/27 ,  H01L29/66 ,  H01L29/792 ,  H10B43/20 ,  H01L21/223 ,  H01L21/265 ,  H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

CPC classification number: H10B43/27 ,  H01L21/223 ,  H01L21/265 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/792 ,  H01L29/7926 ,  H10B43/20

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

公开(公告)号：US11462556B2

公开(公告)日：2022-10-04

申请号：US17071332

申请日：2020-10-15

Applicant: Kioxia Corporation

Inventor： Tetsuya Furukawa ,  Tomoaki Shino ,  Mitsuhiro Noguchi ,  Shinichi Watanabe ,  Yukio Nishida ,  Hiroyasu Tanaka

IPC: H01L27/11573 ,  H01L27/11526 ,  H01L29/49 ,  H01L29/06 ,  H01L29/51 ,  H01L29/423

Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.

公开(公告)号：US11296114B2

公开(公告)日：2022-04-05

申请号：US17335214

申请日：2021-06-01

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki Fukuzumi ,  Shinya Arai ,  Masaki Tsuji ,  Hideaki Aochi ,  Hiroyasu Tanaka

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US11257842B2

公开(公告)日：2022-02-22

申请号：US16849457

申请日：2020-04-15

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC: H01L29/76 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11578 ,  H01L21/223 ,  H01L21/265 ,  H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.