公开(公告)号：US20220173124A1

公开(公告)日：2022-06-02

申请号：US17672819

申请日：2022-02-16

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Shinya Arai ,  Masaki Tsuji ,  Hideaki Aochi ,  Hiroyasu Tanaka

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US20230005958A1

公开(公告)日：2023-01-05

申请号：US17942249

申请日：2022-09-12

Applicant: Kioxia Corporation

Inventor： Masaki Tsuji ,  Yoshiaki Fukuzumi

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11531 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11597

Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection.
The second portion has a width wider than the first portion.

公开(公告)号：US11296114B2

公开(公告)日：2022-04-05

申请号：US17335214

申请日：2021-06-01

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki Fukuzumi ,  Shinya Arai ,  Masaki Tsuji ,  Hideaki Aochi ,  Hiroyasu Tanaka

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US12089410B2

公开(公告)日：2024-09-10

申请号：US18348418

申请日：2023-07-07

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Shinya Arai ,  Masaki Tsuji ,  Hideaki Aochi ,  Hiroyasu Tanaka

IPC: H10B43/27 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H10B43/10 ,  H10B43/50

CPC classification number: H10B43/27 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/50

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US11765904B2

公开(公告)日：2023-09-19

申请号：US17942249

申请日：2022-09-12

Applicant: Kioxia Corporation

Inventor： Masaki Tsuji ,  Yoshiaki Fukuzumi

IPC: H01L27/11582 ,  H10B43/27 ,  H01L29/66 ,  H01L29/792 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B41/42 ,  H10B43/10 ,  H10B43/20 ,  H10B51/20

CPC classification number: H10B43/27 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B41/42 ,  H10B43/10 ,  H10B43/20 ,  H10B51/20

Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.

公开(公告)号：US12219766B2

公开(公告)日：2025-02-04

申请号：US18446579

申请日：2023-08-09

Applicant: Kioxia Corporation

Inventor： Masaki Tsuji ,  Yoshiaki Fukuzumi

IPC: H10B43/27 ,  H01L29/66 ,  H01L29/792 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B41/42 ,  H10B43/10 ,  H10B43/20 ,  H10B51/20

Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.

公开(公告)号：US11980031B2

公开(公告)日：2024-05-07

申请号：US17128915

申请日：2020-12-21

Applicant: Kioxia Corporation

Inventor： Takashi Ishida ,  Yoshiaki Fukuzumi ,  Takayuki Okada ,  Masaki Tsuji

IPC: H01L29/792 ,  H01L21/336 ,  H01L27/115 ,  H01L29/10 ,  H01L29/423 ,  H01L29/788 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L29/1037 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/35

Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

公开(公告)号：US11744075B2

公开(公告)日：2023-08-29

申请号：US17672819

申请日：2022-02-16

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Shinya Arai ,  Masaki Tsuji ,  Hideaki Aochi ,  Hiroyasu Tanaka

IPC: H10B43/27 ,  H01L29/66 ,  H01L29/792 ,  H10B43/10 ,  H10B43/50 ,  H01L29/423

CPC classification number: H10B43/27 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/50

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US11482537B2

公开(公告)日：2022-10-25

申请号：US16940472

申请日：2020-07-28

Applicant: Kioxia Corporation

Inventor： Masaki Tsuji ,  Yoshiaki Fukuzumi

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11531 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11597

Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.