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    SEMICONDUCTOR MEMORY DEVICE
    11.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240096413A1

    公开(公告)日：2024-03-21

    申请号：US18177704

    申请日：2023-03-02

    Applicant: Kioxia Corporation

    Inventor： Natsuki SAKAGUCHI ,  Takashi MAEDA ,  Rieko FUNATSUKI ,  Hidehiro SHIGA

    IPC: G11C16/04 ,  G11C7/06 ,  G11C16/24

    CPC classification number: G11C16/0433 ,  G11C7/065 ,  G11C16/24

    Abstract: A control circuit of a semiconductor memory device performs a write operation on a memory cell transistor of the semiconductor memory device by performing a first pulse application operation of lowering a threshold voltage of the memory cell transistor, a precharge operation, and then a second pulse application operation. In the precharge operation, in a state in which first and second select transistors connected to the memory cell transistor are turned on, a bit line connected to the memory cell transistor is charged by applying a ground voltage to a word line connected to a gate of the memory cell transistor and applying a voltage higher than the ground voltage to a source line. In the second pulse application operation, in a state in which the first select transistor is turned on and the second select transistor is turned off, a program voltage is applied to the word line.

    SEMICONDUCTOR STORAGE DEVICE
    13.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权

    公开(公告)号：US20220301643A1

    公开(公告)日：2022-09-22

    申请号：US17459441

    申请日：2021-08-27

    Applicant: KIOXIA CORPORATION

    Inventor： Rieko FUNATSUKI ,  Takashi MAEDA ,  Reiko SUMI ,  Reika TANAKA ,  Masumi SAITOH

    IPC: G11C16/34 ,  G11C16/14 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C16/08

    Abstract: A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.

    SEMICONDUCTOR MEMORY DEVICE
    14.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220301636A1

    公开(公告)日：2022-09-22

    申请号：US17447464

    申请日：2021-09-13

    Applicant: Kioxia Corporation

    Inventor： Kyosuke SANO ,  Kazutaka IKEGAMI ,  Takashi MAEDA ,  Rieko FUNATSUKI

    IPC: G11C16/26 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/30

    Abstract: A semiconductor memory device of embodiments includes: a substrate; a memory pillar; first to sixth conductive layers provided above the substrate; first to sixth memory cells formed between the first to sixth conductive layers and the memory pillar, respectively; and a control circuit. The control circuit applies a first voltage to the first, second, a sixth conductive layer and applies a second voltage to the third, fifth conductive layer, then applies a third voltage to the first conductive layer, applies a fourth voltage to the sixth conductive layer, and applies a fifth voltage to the second conductive layer, and then applies a sixth voltage to the first conductive layer, applies a seventh voltage to the sixth conductive layer, and applies an eighth voltage lower than the fifth voltage to the second conductive layer.

    SEMICONDUCTOR STORAGE DEVICE
    15.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权

    公开(公告)号：US20220301632A1

    公开(公告)日：2022-09-22

    申请号：US17459328

    申请日：2021-08-27

    Applicant: KIOXIA CORPORATION

    Inventor： Takashi MAEDA

    IPC: G11C16/14 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C29/42

    Abstract: A semiconductor storage device includes a memory cell array including memory cell transistors connected in series between a bit line and a source line and word lines respectively connected to gates of the memory cell transistors. In the erasing operation to erase data stored in a selected memory cell transistor, while an erase voltage is applied to the bit line and the source line: a first voltage is applied to the word line connected to the gate of the selected memory cell transistor, a second voltage higher than the first voltage is applied to the word line connected to the gate of each memory cell transistor adjacent to the selected memory cell transistor, and a third voltage higher than the second voltage and lower than the erase voltage is applied to the word line connected to the gate of each memory cell transistor not adjacent to the selected memory cell transistor.

    SEMICONDUCTOR MEMORY DEVICE
    18.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200381067A1

    公开(公告)日：2020-12-03

    申请号：US16783782

    申请日：2020-02-06

    Applicant: KIOXIA CORPORATION

    Inventor： Takashi MAEDA

    IPC: G11C16/34 ,  G11C5/06 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11582

    Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell and a second memory cell capable of storing data and coupled in parallel to a bit line; a first word line coupled to the first memory cell; a second word line coupled to the second memory cell and being different from the first word line; and a control circuit. The first memory cell and the second memory cell share a first well region and are opposed to each other, with the first well region interposed. The control circuit is configured, in a first operation, to repeat application of a first voltage to the first word line and the second word line a plurality of times while increasing the first voltage.

    INFORMATION PROCESSING APPARATUS AND MEMORY SYSTEM
    19.
    发明公开
    INFORMATION PROCESSING APPARATUS AND MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240311286A1

    公开(公告)日：2024-09-19

    申请号：US18601791

    申请日：2024-03-11

    Applicant: Kioxia Corporation

    Inventor： Atsushi KAWASUMI ,  Takashi MAEDA ,  Hidehiro SHIGA

    IPC: G06F12/02 ,  G11C16/04 ,  G11C16/26

    CPC classification number: G06F12/02 ,  G11C16/0483 ,  G11C16/26 ,  G06F2212/10

    Abstract: An information processing apparatus that detects whether the corresponding first element and second element among the multiple first elements and the plurality of second elements are matched or are similar, has one or multiple strings connected to a first wiring and connected to multiple second wirings, wherein the string includes multiple transistor pairs connected in series along a current path having one end connected to the first wiring, each of the multiple transistor pairs includes a first transistor and a second transistor connected in series along the current path, the second wirings are connected to gates of the first transistor and the second transistor in each of the multiple transistor pairs, the first transistor is set to a first threshold depending on first data, the second transistor is set to a second threshold depending on second data that is complement data of the first data.

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