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    Memory system
    12.
    发明授权
    Memory system 有权

    公开(公告)号：US11442808B2

    公开(公告)日：2022-09-13

    申请号：US17198451

    申请日：2021-03-11

    Applicant: Kioxia Corporation

    Inventor： Takehiko Amaki ,  Toshikatsu Hida ,  Shunichi Igahara ,  Yoshihisa Kojima ,  Suguru Nishikawa

    IPC: G11C29/00 ,  G06F11/10 ,  G06F12/0891 ,  G06F12/02 ,  G06F11/07

    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n−1 data portions of a first unit that are included in n−1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n−1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n−1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.

    Memory system including non-volatile buffer and control method thereof
    13.
    发明授权
    Memory system including non-volatile buffer and control method thereof 有权

    公开(公告)号：US11436136B2

    公开(公告)日：2022-09-06

    申请号：US16807275

    申请日：2020-03-03

    Applicant: Kioxia Corporation

    Inventor： Takehiko Amaki ,  Toshikatsu Hida ,  Shunichi Igahara ,  Yoshihisa Kojima ,  Suguru Nishikawa

    IPC: G06F12/02 ,  G06F3/06

    Abstract: According to one embodiment, a memory system includes a non-volatile memory including first and second block groups, and a controller that performs a first write operation for the first block group and the first or a second write operation for the second block group. A first or second number of bits is written into a memory cell in the first or the second write operation. The second number of bits is larger than the first number of bits. The controller allocates a block to a buffer as a write destination block in the first write operation based on a degree of wear-out of at least one block, and writes data from an external device into the buffer in the first write operation.

    Memory system and control method
    15.
    发明授权
    Memory system and control method 有权

    公开(公告)号：US11789643B2

    公开(公告)日：2023-10-17

    申请号：US17685229

    申请日：2022-03-02

    Applicant: KIOXIA CORPORATION

    Inventor： Suguru Nishikawa ,  Toshikatsu Hida ,  Shunichi Igahara ,  Takehiko Amaki

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0608 ,  G06F3/0619 ,  G06F3/0679

    Abstract: According to one embodiment, a memory system includes non-volatile memory and volatile memory. A controller encodes a first unit size data portion to be written into the non-volatile memory and generates a first error correction code for the data portion, then writes the data portion into the non-volatile memory. The controller also stores the first error correction code in the volatile memory. When non-volatilization of an error correction code protect the data portion is requested, the controller encodes the data portion to generate a second error correction code for the data portion, and then writes the second error correction code into the non-volatile memory. The second error correction code is smaller in size than the first error correction code.

    Semiconductor memory medium and memory system
    17.
    发明授权
    Semiconductor memory medium and memory system 有权

    公开(公告)号：US11244728B2

    公开(公告)日：2022-02-08

    申请号：US17018147

    申请日：2020-09-11

    Applicant: Kioxia Corporation

    Inventor： Suguru Nishikawa ,  Takehiko Amaki ,  Yoshihisa Kojima ,  Shunichi Igahara

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

    Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

    Reading of start-up information from different memory regions of a memory system
    18.
    发明授权
    Reading of start-up information from different memory regions of a memory system 有权

    公开(公告)号：US11042310B2

    公开(公告)日：2021-06-22

    申请号：US16506475

    申请日：2019-07-09

    Applicant: KIOXIA CORPORATION

    Inventor： Riki Suzuki ,  Toshikatsu Hida ,  Takehiko Amaki ,  Shunichi Igahara

    IPC: G06F3/06 ,  G06F11/10 ,  G11C29/00 ,  G06F12/02 ,  G06F12/0875 ,  G11C29/52

    Abstract: A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.

    Memory system
    20.
    发明授权
    Memory system 有权

    公开(公告)号：US11740965B2

    公开(公告)日：2023-08-29

    申请号：US17519356

    申请日：2021-11-04

    Applicant: KIOXIA CORPORATION

    Inventor： Shunichi Igahara ,  Yoshihisa Kojima ,  Takehiko Amaki ,  Suguru Nishikawa

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1068 ,  G06F3/0679 ,  G06F11/1044 ,  G06F11/1056

    Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.

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