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    Hybrid Phase Unwrapping Systems and Methods for Patterned Wafer Measurement
    11.
    发明申请
    Hybrid Phase Unwrapping Systems and Methods for Patterned Wafer Measurement 有权
    混合相位展开系统和图形晶片测量方法

    公开(公告)号：US20160321799A1

    公开(公告)日：2016-11-03

    申请号：US14808994

    申请日：2015-07-24

    Applicant: KLA-Tencor Corporation

    Inventor： Haiguang Chen ,  Jaydeep Sinha

    IPC: G06T7/00 ,  G01N21/95 ,  G01N21/88 ,  G01B11/24 ,  G01B11/06

    CPC classification number: G01N21/9501 ,  G01B11/06 ,  G01B11/2441 ,  G01N21/8851 ,  G01N2201/06113 ,  G01N2201/12 ,  G06T7/0004 ,  G06T2207/10056 ,  G06T2207/30148

    Abstract: Systems and methods for unwrapping phase signals obtained from interferometry measurements of patterned wafer surfaces are disclosed. A phase unwrapping method in accordance with the present disclosure may calculate a front surface phase map and a back surface phase map of a wafer, subtract the back surface phase map from the front surface phase map to obtain a phase difference map, unwrap the phase difference map to obtain a wafer thickness variation map, unwrap the back surface phase map to obtain a back surface map representing the back surface of the wafer; and add the wafer thickness variation map to the back surface phase map to calculate a front surface map representing the front surface of the wafer.

    Abstract translation: 公开了用于展开由图案化晶片表面的干涉测量获得的相位信号的系统和方法。 根据本公开的相位展开方法可以计算晶片的前表面相位图和背面相位图，从前表面相位图中减去背面相位图以获得相位差图，展开相位差 映射以获得晶片厚度变化图，展开背面相位图以获得表示晶片背面的背面图; 并将晶片厚度变化图添加到背面相位图以计算表示晶片前表面的前表面图。

    System and Method to Emulate Finite Element Model Based Prediction of In-Plane Distortions Due to Semiconductor Wafer Chucking
    12.
    发明申请
    System and Method to Emulate Finite Element Model Based Prediction of In-Plane Distortions Due to Semiconductor Wafer Chucking 有权
    基于有限元模型的半导体晶片卡盘的平面失真预测的系统和方法

    公开(公告)号：US20140107998A1

    公开(公告)日：2014-04-17

    申请号：US13735737

    申请日：2013-01-07

    Applicant: KLA-Tencor Corporation

    Inventor： Pradeep Vukkadala ,  Sathish Veeraraghavan ,  Jaydeep Sinha ,  Haiguang Chen ,  Michael Kirk

    IPC: G06F17/50

    CPC classification number: G06F17/5018 ,  H01L21/67288

    Abstract: Systems and methods for prediction of in-plane distortions (IPD) due to wafer shape in semiconductor wafer chucking process is disclosed. A process to emulate the non-linear finite element (FE) contact mechanics model based IPD prediction is utilized in accordance with one embodiment of the present disclosure. The emulated FE model based prediction process is substantially more efficient and provides accuracy comparable to the FE model based IPD prediction that utilizes full-scale 3-D wafer and chuck geometry information and requires computation intensive simulations. Furthermore, an enhanced HOS IPD/OPD prediction process based on a series of Zernike basis wafer shape images is also disclosed.

    Abstract translation: 公开了用于预测半导体晶片夹持工艺中的晶片形状的面内失真（IPD）的系统和方法。 根据本公开的一个实施例，利用仿真基于IPD预测的非线性有限元（FE）接触力学模型的过程。 基于模拟的基于有限元模型的预测过程基本上更有效，并且提供了与使用全尺寸3-D晶片和卡盘几何信息的基于有限元模型的基于有限元模型的预测相当的精度，并且需要计算密集模拟。 此外，还公开了基于一系列Zernike基晶片形状图像的增强型HOS IPD / OPD预测处理。

    Systems and Methods of Advanced Site-Based Nanotopography for Wafer Surface Metrology
    13.
    发明申请
    Systems and Methods of Advanced Site-Based Nanotopography for Wafer Surface Metrology 有权
    用于晶圆表面计量的先进的基于位点的纳米形貌的系统和方法

    公开(公告)号：US20130236085A1

    公开(公告)日：2013-09-12

    申请号：US13779947

    申请日：2013-02-28

    Applicant: KLA-TENCOR CORPORATION

    Inventor： Haiguang Chen ,  Sergey Kamensky ,  Jaydeep Sinha ,  Pradeep Vukkadala

    IPC: G06T7/00

    CPC classification number: G06T7/0004 ,  G06T5/20 ,  G06T2207/20021 ,  G06T2207/30148

    Abstract: Systems and methods for providing micro defect inspection capabilities for optical systems are disclosed. Each given wafer image is filtered, treated and normalized prior to performing surface feature detection and quantification. A partitioning scheme is utilized to partition the wafer image into a plurality of measurement sites and metric values are calculated for each of the plurality of measurement sites. Furthermore, transformation steps may also be utilized to extract additional process relevant metric values for analysis purposes.

    Abstract translation: 公开了用于为光学系统提供微缺陷检测能力的系统和方法。 在进行表面特征检测和定量之前，对每个给定的晶片图像进行过滤，处理和归一化。 利用分割方案将晶片图像分割成多个测量位置，并且为多个测量位置中的每一个计算度量值。 此外，为了分析目的，转换步骤也可以用于提取附加的过程相关度量值。

    Systems, Methods and Metrics for Wafer High Order Shape Characterization and Wafer Classification Using Wafer Dimensional Geometry Tool
    19.
    发明申请
    Systems, Methods and Metrics for Wafer High Order Shape Characterization and Wafer Classification Using Wafer Dimensional Geometry Tool 有权
    使用晶圆尺寸几何工具的晶圆高阶形状表征和晶圆分类的系统，方法和度量

    公开(公告)号：US20140114597A1

    公开(公告)日：2014-04-24

    申请号：US13656143

    申请日：2012-10-19

    Applicant: KLA-Tencor Corporation

    Inventor： Haiguang Chen ,  Jaydeep Sinha ,  Sergey Kamensky ,  Sathish Veeraraghavan ,  Pradeep Vukkadala

    IPC: G01B11/24 ,  G06F17/00

    CPC classification number: G01B11/24 ,  G01B2210/56 ,  G01N21/9501 ,  G06F17/00 ,  H01L22/12

    Abstract: Systems and methods for improving results of wafer higher order shape (HOS) characterization and wafer classification are disclosed. The systems and methods in accordance with the present disclosure are based on localized shapes. A wafer map is partitioned into a plurality of measurement sites to improve the completeness of wafer shape representation. Various site based HOS metric values may be calculated for wafer characterization and/or classification purposes, and may also be utilized as control input for a downstream application. In addition, polar grid partitioning schemes are provided. Such polar grid partitioning schemes may be utilized to partition a wafer surface into measurement sites having uniform site areas while providing good wafer edge region coverage.

    Abstract translation: 公开了用于改善晶片高阶形状（HOS）表征和晶片分类的结果的系统和方法。 根据本公开的系统和方法基于局部形状。 将晶片图划分成多个测量点，以提高晶片形状表示的完整性。 可以针对晶片表征和/或分类目的计算各种基于站点的HOS度量值，并且还可以用作下游应用的控制输入。 此外，还提供了极坐标分割方案。 可以利用这种极性栅格划分方案将晶片表面划分成具有均匀位置区域的测量位置，同时提供良好的晶片边缘区域覆盖。

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