利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

232 条记录 (耗时 0.024 秒)

    SIMULTANEOUSLY FORMING HIGH-SPEED AND LOW-POWER MEMORY DEVICES ON A SINGLE SUBSTRATE
    11.
    发明申请
    SIMULTANEOUSLY FORMING HIGH-SPEED AND LOW-POWER MEMORY DEVICES ON A SINGLE SUBSTRATE 审中-公开
    同时在单个基板上同时形成高速和低功耗存储器件

    公开(公告)号：US20080160713A1

    公开(公告)日：2008-07-03

    申请号：US11617960

    申请日：2006-12-29

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

    IPC分类号： H01L21/28

    CPC分类号： H01L27/1203 ,  H01L27/0733 ,  H01L27/1207 ,  H01L29/945

    摘要： A method patterns a trench mask over both SOI regions and bulk silicon regions of a single substrate. Next, the SOI regions and the bulk silicon regions are simultaneously etched through the trench mask to form trenches in the SOI regions and the bulk silicon regions. In such processing the buried insulating layer in SOI regions causes trenches within the SOI regions to be less deep (more shallow) than trenches in the bulk silicon regions (which are deeper or less shallow). After the trenches are formed, the method completes the process by forming capacitors in the trenches. More specifically, the method simultaneously lines all of the trenches with an insulator and simultaneously fills all of the trenches with a conductor to form capacitors in the trenches. The capacitors within the SOI regions have a lower capacitance that the capacitors within the SOI regions.

    摘要翻译： 一种方法在单个衬底的SOI区域和体硅区域上形成沟槽掩模。 接下来，通过沟槽掩模同时蚀刻SOI区域和体硅区域，以在SOI区域和体硅区域中形成沟槽。 在这种处理中，SOI区域中的掩埋绝缘层使得SOI区域内的沟槽比体硅区域（更深或更浅）中的沟槽更深（更浅）。 在沟槽形成之后，该方法通过在沟槽中形成电容器来完成该工艺。 更具体地，该方法同时用绝缘体对所有沟槽进行排列，同时用导体填充所有沟槽，以在沟槽中形成电容器。 SOI区域内的电容器具有较低的电容，即SOI区域内的电容器。

    SOI device with different crystallographic orientations
    12.
    发明授权
    SOI device with different crystallographic orientations 失效
    具有不同晶体取向的SOI器件

    公开(公告)号：US07132324B2

    公开(公告)日：2006-11-07

    申请号：US10905002

    申请日：2004-12-09

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

    IPC分类号： H01L21/8242 ,  H01L21/20

    CPC分类号： H01L29/78642 ,  H01L27/10864 ,  H01L27/1087

    摘要： A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the lithographic pattern for the active area, in particular a DRAM cell with a vertical transistor.

    摘要翻译： 在半导体衬底中形成具有沟槽电容器和垂直晶体管的存储单元的方法包括提供具有平行于第一晶片轴的[010]轴的下基板的接合半导体晶片的步骤，以及具有 相对于晶片轴线定向成四十五度的[010]轴，两者通过一层粘合绝缘体连接; 蚀刻通过上层和下衬底的沟槽; 扩大沟槽的下部并将沟槽的上部的横截面从八边形转换为矩形，从而降低对沟槽光刻和有源区光刻之间对准误差的敏感性。 替代方案采用具有由（111）晶体结构和相同上部形成的下基板的键合半导体晶片。 应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻图案之间的未对准变得不敏感的垂直晶体管。

    Trench optical device
    13.
    发明授权
    Trench optical device 有权
    沟槽光学器件

    公开(公告)号：US06943409B1

    公开(公告)日：2005-09-13

    申请号：US10709699

    申请日：2004-05-24

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

    IPC分类号： H01L29/76

    CPC分类号： B82Y20/00 ,  H01L27/1446 ,  H01L31/03529 ,  H01L31/105 ,  H01L31/1804 ,  Y02E10/547

    摘要： A semiconductor device is formed in on a semiconductor substrate starting with a first step, which is to form a wide trench and a narrow trench in the substrate. Then form a first electrode in the narrow trench by depositing a first fill material of a first conductivity type over the device to fill the wide trench partially and to fill the narrow trench completely. Etch back the first fill material until completion of removal thereof from the wide trench. Form a second electrode in the wide trench by filling the wide trench with a second fill material of an opposite conductivity type. Anneal to drive dopant both from the first fill material of the first electrode into a first outdiffusion region in the substrate about the periphery of the narrow trench and from the second fill material of the second electrode into a second outdiffusion region in the substrate about the periphery of the wide trench.

    摘要翻译： 半导体器件形成在半导体衬底上，从第一步骤开始，其在衬底中形成宽沟槽和窄沟槽。 然后通过在器件上沉积第一导电类型的第一填充材料，以便部分填充宽沟槽并完全填充窄沟槽，在窄沟槽中形成第一电极。 将第一填充材料回扫，直到完成从宽沟槽中移除。 通过用相反导电类型的第二填充材料填充宽沟槽在宽沟槽中形成第二电极。 退火以将掺杂剂从第一电极的第一填充材料驱动到衬底周围的窄沟槽的第一外扩散区域中，并且从第二电极的第二填充材料移动到衬底周围的第二外扩散区域 的宽沟。

    Integration of fin-based devices and ETSOI devices
    14.
    发明授权
    Integration of fin-based devices and ETSOI devices 有权
    集成了鳍式设备和ETSOI设备

    公开(公告)号：US08236634B1

    公开(公告)日：2012-08-07

    申请号：US13050023

    申请日：2011-03-17

    申请人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

    发明人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

    IPC分类号： H01L27/088

    CPC分类号： H01L27/1211 ,  H01L21/845

    摘要： Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.

    摘要翻译： 薄半导体区域和厚半导体区域被形成为绝缘体层。 厚半导体区域包括至少一个半导体鳍片。 图案化栅极导体层以在半导体鳍片的侧壁上的ETSOI区域和一次侧栅电极上形成一次性平面栅电极。 半导体翅片的端部垂直凹入，以提供与未固定的翅片中心部分相邻的变薄的翅片部分。 在通过介电层适当掩蔽之后，在ETSOI场效应晶体管（FET）的平面源极和漏极区域上进行选择性外延以形成升高的源极和漏极区域。 此外，翅片源极和漏极区域在薄的鳍部上生长。 源极和漏极区域，鳍片和一次性栅电极被平坦化。 一次性栅电极被金属栅电极代替。 FinFET和ETSOI FET设置在相同的半导体衬底上。

    Dual port gain cell with side and top gated read transistor
    15.
    发明授权
    Dual port gain cell with side and top gated read transistor 失效
    双端口增益单元，具有侧和顶栅控读取晶体管

    公开(公告)号：US07790530B2

    公开(公告)日：2010-09-07

    申请号：US12254960

    申请日：2008-10-21

    申请人： Jack A. Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Geng Wang

    发明人： Jack A. Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Geng Wang

    IPC分类号： H01L21/00

    CPC分类号： H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

    摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

    摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

    INTEGRATION OF FIN-BASED DEVICES AND ETSOI DEVICES
    17.
    发明申请
    INTEGRATION OF FIN-BASED DEVICES AND ETSOI DEVICES 有权
    基于FIN的设备和ETSOI设备的集成

    公开(公告)号：US20120261756A1

    公开(公告)日：2012-10-18

    申请号：US13530887

    申请日：2012-06-22

    申请人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

    发明人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

    IPC分类号： H01L27/12

    CPC分类号： H01L27/1211 ,  H01L21/845

    摘要： Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.

    摘要翻译： 薄半导体区域和厚半导体区域被形成为绝缘体层。 厚半导体区域包括至少一个半导体鳍片。 图案化栅极导体层以在半导体鳍片的侧壁上的ETSOI区域和一次侧栅电极上形成一次性平面栅电极。 半导体翅片的端部垂直凹入，以提供与未固定的翅片中心部分相邻的变薄的翅片部分。 在通过介电层适当掩蔽之后，在ETSOI场效应晶体管（FET）的平面源极和漏极区域上进行选择性外延以形成升高的源极和漏极区域。 此外，翅片源极和漏极区域在薄的鳍部上生长。 源极和漏极区域，鳍片和一次性栅电极被平坦化。 一次性栅电极被金属栅电极代替。 FinFET和ETSOI FET设置在相同的半导体衬底上。

    Simplified buried plate structure and process for semiconductor-on-insulator chip
    18.
    发明授权
    Simplified buried plate structure and process for semiconductor-on-insulator chip 有权
    半导体绝缘体芯片的简化掩埋板结构和工艺

    公开(公告)号：US08053823B2

    公开(公告)日：2011-11-08

    申请号：US10906808

    申请日：2005-03-08

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Herbert L. Ho ,  Carl J. Radens

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Herbert L. Ho ,  Carl J. Radens

    IPC分类号： H01L27/108

    CPC分类号： H01L21/84 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

    摘要： A structure is provided herein which includes an array of trench capacitors having at least portions disposed below a buried oxide layer of an SOI substrate. Each trench capacitor shares a common unitary buried capacitor plate which includes at least a portion of a first unitary semiconductor region disposed below the buried oxide layer. An upper boundary of the buried capacitor plate defines a plane parallel to a major surface of the substrate which extends laterally throughout the array of trench capacitors. In a particular embodiment, which starts from either an SOI or a bulk substrate, trenches of the array and a contact hole are formed simultaneously, such that the contact hole extends to substantially the same depth as the trenches. The contact hole preferably has substantially greater width than the trenches such that the conductive contact via can be formed simultaneously by processing used to form trench capacitors extending along walls of the trenches.

    摘要翻译： 本文提供了一种结构，其包括具有设置在SOI衬底的掩埋氧化物层下方的至少部分的沟槽电容器阵列。 每个沟槽电容器共享共同的单一掩埋电容器板，其包括设置在掩埋氧化物层下方的第一单一半导体区域的至少一部分。 掩埋电容器板的上边界限定平行于衬底的主表面的平面，横向延伸穿过整个沟槽电容器阵列。 在从SOI或体衬底开始的特定实施例中，阵列的沟槽和接触孔同时形成，使得接触孔延伸到与沟槽基本相同的深度。 接触孔优选地具有比沟槽更大的宽度，使得可以通过用于形成沿着沟槽的壁延伸的沟槽电容器的处理同时形成导电接触通孔。

    DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR
    20.
    发明申请
    DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 失效
    双端口增益单元与侧面和顶部读取晶体管

    公开(公告)号：US20090047756A1

    公开(公告)日：2009-02-19

    申请号：US12254960

    申请日：2008-10-21

    申请人： Jack A. Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Geng Wang

    发明人： Jack A. Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Geng Wang

    IPC分类号： H01L21/84 ,  H01L21/8242

    CPC分类号： H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

    摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

    摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。