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206 条记录 (耗时 0.043 秒)

    Laminated polyester film
    12.
    发明授权
    Laminated polyester film 失效
    层压聚酯薄膜

    公开(公告)号：US06306492B1

    公开(公告)日：2001-10-23

    申请号：US08997459

    申请日：1997-12-23

    申请人： Koji Yamada ,  Yasushi Sasaki ,  Toshitake Suzuki ,  Shinya Higashiura ,  Chikao Morishige

    发明人： Koji Yamada ,  Yasushi Sasaki ,  Toshitake Suzuki ,  Shinya Higashiura ,  Chikao Morishige

    IPC分类号： B32B518

    CPC分类号： C08J7/047 ,  B32B27/36 ,  C08J2367/02 ,  C08J2451/00 ,  Y10S428/91 ,  Y10T428/249985 ,  Y10T428/249992 ,  Y10T428/265 ,  Y10T428/273 ,  Y10T428/31786

    摘要： A laminated polyester film comprising a polyester base film and a layer comprising a polyester graft copolymer and which is formed at least on one surface of said polyester base film, said polyester graft copolymer comprising a hydrophobic copolymerizable polyester resin and an acid anhydride having at least one double bond grafted to said polyester resin. The laminated polyester film of the present invention exhibits good adhesive property, water resistance and resistance to blocking, particularly excellent adhesive property, by applying a specific polyester graft copolymer to a polyester base film.

    摘要翻译： 一种层叠聚酯膜，其包含聚酯基膜和包含聚酯接枝共聚物的层，并且其形成在所述聚酯基膜的至少一个表面上，所述聚酯接枝共聚物包含疏水性可共聚聚酯树脂和具有至少一个 双键接枝到所述聚酯树脂上。 本发明的层叠聚酯薄膜通过将特定的聚酯接枝共聚物涂布在聚酯基膜上，具有良好的粘合性，耐水性和耐粘连性，特别优异的粘合性。

    Recording material
    14.
    发明授权
    Recording material 失效
    录音材料

    公开(公告)号：US06605337B1

    公开(公告)日：2003-08-12

    申请号：US09558633

    申请日：2000-04-26

    申请人： Kenichi Mori ,  Kazuyuki Tsuchiiwa ,  Katsuya Ito ,  Toru Kotani ,  Yasushi Sasaki

    发明人： Kenichi Mori ,  Kazuyuki Tsuchiiwa ,  Katsuya Ito ,  Toru Kotani ,  Yasushi Sasaki

    IPC分类号： B32B2714

    CPC分类号： B41M5/52 ,  B41M3/008 ,  B41M5/506 ,  B41M5/508 ,  B41M5/5218 ,  B41M5/5227 ,  B41M5/5272 ,  Y10T428/24802 ,  Y10T428/24893 ,  Y10T428/26 ,  Y10T428/31786

    摘要： A recording material comprising a substrate and an ink receiving layer formed thereon, wherein said substrate has a thickness of 38-200 &mgr;m, said ink receiving layer is a porous layer comprising particles and a resin and has a thickness of not less than 40 &mgr;m and not more than 105 &mgr;m, and wherein the recording material has a curl value of not more than +10 mm, and a recording material comprising a substrate and an ink absorption layer formed thereon, wherein the ink absorption layer has a surface strength of not less than 80 g weight/cm. The recording material thus obtained affords sharp recording of images having extremely high water resistance and free of bleeding by the ink jet recording method particularly using oily ink. The material hardly curls even under severe environment associated with radically changing humidity, temperature and the like, thereby ensuring stable transportability of the recording material without trouble caused by being in contact with a priting head. When used as an illumination signboard, moreover, the recording material affords superior images that are maintained when the illumination signboard is on or off.

    摘要翻译： 一种记录材料，包括在其上形成的基材和油墨接收层，其中所述基材具有38-200μm的厚度，所述油墨接收层是包含颗粒和树脂的多孔层，并且具有不小于40μm的厚度和 不大于105μm，并且其中所述记录材料具有不大于+ 10mm的卷曲值，以及包含基底和形成在其上的墨吸收层的记录材料，其中所述墨吸收层的表面强度不小于 超过80g重量/厘米。 由此获得的记录材料通过喷墨记录方法特别是使用油性油墨提供了具有极高耐水性和无渗色的图像的清晰记录。 即使在与湿度，温度等急剧变化相关联的严酷环境下，材料也难以卷曲，从而确保了记录材料的稳定的运输性，而不会由于与头部接触而引起麻烦。 此外，当用作照明招牌时，记录材料提供当照明招牌打开或关闭时保持的优质图像。

    Display driving circuit, display panel and display device
    16.
    发明授权
    Display driving circuit, display panel and display device 有权
    显示驱动电路，显示面板和显示设备

    公开(公告)号：US08970565B2

    公开(公告)日：2015-03-03

    申请号：US13378233

    申请日：2010-03-18

    申请人： Takuya Hachida ,  Yuhichiroh Murakami ,  Shige Furuta ,  Makoto Yokoyama ,  Yasushi Sasaki

    发明人： Takuya Hachida ,  Yuhichiroh Murakami ,  Shige Furuta ,  Makoto Yokoyama ,  Yasushi Sasaki

    IPC分类号： G06F3/038 ,  G09G3/36 ,  G11C19/28

    CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2310/063

    摘要： A stage of the shift register has (i) a set-reset type flip-flop which receives an initialization signal and (ii) a signal generating circuit which receives a simultaneous selection signal and which generates an output signal by use of an output of the flip-flop. In at least one example embodiment, the output of the flip-flop becomes inactive regardless of whether a setting signal and a resetting signal are active or inactive, as long as the initialization signal is active. The initialization signal becomes active before the end of the simultaneous selection, and then becomes inactive after the end of the simultaneous selection. This makes it possible to stabilize operation of the shift register after the end of simultaneous selection of a plurality of signal lines carried out by the display driving circuit at a predetermined timing.

    摘要翻译： 移位寄存器的一级具有（i）接收初始化信号的设置复位型触发器，以及（ii）接收同时选择信号并且通过使用输出信号产生输出信号的信号发生电路 拖鞋。 在至少一个示例性实施例中，只要初始化信号有效，触发器的输出就会变得无效，而不管设置信号和复位信号是有效还是无效。 初始化信号在同时选择结束之前变为有效，然后在同时选择结束后变为无效。 这使得可以在预定定时同时选择由显示驱动电路执行的多条信号线结束之后稳定移位寄存器的操作。

    Signal processing circuit, inverter circuit, buffer circuit, level shifter, flip-flop, driver circuit, and display device
    17.
    发明授权
    Signal processing circuit, inverter circuit, buffer circuit, level shifter, flip-flop, driver circuit, and display device 有权
    信号处理电路，逆变电路，缓冲电路，电平转换器，触发器，驱动电路和显示装置

    公开(公告)号：US08779809B2

    公开(公告)日：2014-07-15

    申请号：US13819400

    申请日：2011-08-31

    申请人： Yuhichiroh Murakami ,  Yasushi Sasaki ,  Etsuo Yamamoto

    发明人： Yuhichiroh Murakami ,  Yasushi Sasaki ,  Etsuo Yamamoto

    IPC分类号： H03K3/00

    CPC分类号： H02J4/00 ,  H03K3/356008 ,  H03K3/356026 ,  H03K19/01714 ,  H03K19/01735 ,  Y10T307/50

    摘要： A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; and an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal, the electric charge control section and the first output section being connected to each other via a relay section for either electrically connecting the electric charge control section and the first output section to each other or electrically blocking the electric charge control section and the first output section from each other, the electric charge control section including a resistor connected to a second power source. This configuration can increase reliability of a bootstrap-type signal processing circuit.

    摘要翻译： 本发明的信号处理电路包括：第一和第二输入端; 输出端子; 自举电容器; 与第二输入端子和输出端子连接的第一输出部分; 连接到第一输入端子的第二输出部分，第一电源和输出端子; 以及用于控制自举电容器的电荷的电荷控制部分，所述电荷控制部分连接到所述第一输入端子，所述电荷控制部分和所述第一输出部分经由继电器部分彼此连接，用于任一 将电荷控制部和第一输出部彼此电连接，或者将电荷控制部和第一输出部彼此电阻塞，电荷控制部包括与第二电源连接的电阻。 该配置可以增加自举式信号处理电路的可靠性。

    Active matrix liquid crystal display device and method of driving the same
    18.
    发明授权
    Active matrix liquid crystal display device and method of driving the same 有权
    有源矩阵液晶显示装置及其驱动方法

    公开(公告)号：US08736534B2

    公开(公告)日：2014-05-27

    申请号：US11922491

    申请日：2006-07-11

    申请人： Etsuo Yamamoto ,  Yuhichiroh Murakami ,  Yasushi Sasaki ,  Seijirou Gyouten

    发明人： Etsuo Yamamoto ,  Yuhichiroh Murakami ,  Yasushi Sasaki ,  Seijirou Gyouten

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3648 ,  G09G3/3688 ,  G09G2310/0245 ,  G09G2330/02 ,  G09G2330/027

    摘要： In one embodiment of the present invention, on each source bus line, an electric charge escaping transistor is provided having the same polarity as a pixel transistor and having a gate to which a turn-off voltage signal of the pixel transistor is supplied. When an active matrix liquid crystal display device is powered off, the turn-off voltage signal is made to reach the GND level before a turn-on voltage signal of the pixel transistor reaches the GND level, so that the pixel transistor and the electric charge escaping transistor are made half-open. This lets electric charges accumulated in the pixel escape to a common electrode TCOM.

    摘要翻译： 在本发明的一个实施例中，在每个源极总线上，设置电荷逸出晶体管，其具有与像素晶体管相同的极性，并且具有提供像素晶体管的关断电压信号的栅极。 当有源矩阵液晶显示装置断电时，在像素晶体管的导通电压信号达到GND电平之前，使关断电压信号达到GND电平，使得像素晶体管和电荷 逃逸晶体管制成半开放。 这使得在像素中累积的电荷逃逸到公共电极TCOM。

    Display driving circuit having a memory circuit, display device, and display driving method
    19.
    发明授权
    Display driving circuit having a memory circuit, display device, and display driving method 有权
    具有存储电路，显示装置和显示驱动方法的显示驱动电路

    公开(公告)号：US08547368B2

    公开(公告)日：2013-10-01

    申请号：US12734363

    申请日：2008-09-02

    申请人： Makoto Yokoyama ,  Yasushi Sasaki ,  Yuhichiroh Murakami

    发明人： Makoto Yokoyama ,  Yasushi Sasaki ,  Yuhichiroh Murakami

    IPC分类号： G06F3/038 ,  G09G5/00 ,  G09G3/30 ,  G09G3/36

    CPC分类号： G09G3/3677 ,  G09G3/3655 ,  G09G2300/0876 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0219 ,  G11C19/184

    摘要： A display driving circuit of the present invention includes: a source driver (20) which outputs a source signal; a gate driver (30) which outputs a gate signal for turning on a switching element on a row; and a CS driver (40) which outputs a CS signal (CSOUT) whose electric potential is switched in a predetermined direction (low to high or high to low) in accordance with a polarity of the source signal. A CS driver (CSn) on an n-th row outputs a CS signal (CSOUT) to the n-th row in accordance with a gate signal (GLn) for the n-th row outputted from a gate driver (Gn) provided on the n-th row. This makes it possible to provide a display driving circuit which enables CC driving with a simple configuration.

    摘要翻译： 本发明的显示驱动电路包括：源极驱动器，其输出源极信号; 栅极驱动器（30），其输出用于导通行上的开关元件的栅极信号; 以及CS驱动器（40），其根据源极信号的极性输出电位从规定的方向（低到高或高到低）切换的CS信号（CSOUT）。 第n行的CS驱动器（CSn）根据从设置在第n行的栅极驱动器（Gn）输出的第n行的栅极信号（GLn）向第n行输出CS信号（CSOUT） 第n行。 这使得可以提供一种能够以简单的结构实现CC驱动的显示驱动电路。

    SIGNAL PROCESSING CIRCUIT, INVERTER CIRCUIT, BUFFER CIRCUIT, DRIVER CIRCUIT, LEVEL SHIFTER, AND DISPLAY DEVICE
    20.
    发明申请
    SIGNAL PROCESSING CIRCUIT, INVERTER CIRCUIT, BUFFER CIRCUIT, DRIVER CIRCUIT, LEVEL SHIFTER, AND DISPLAY DEVICE 有权
    信号处理电路，逆变器电路，缓冲电路，驱动电路，电平变换器和显示装置

    公开(公告)号：US20130194033A1

    公开(公告)日：2013-08-01

    申请号：US13819043

    申请日：2011-08-31

    申请人： Yuhichiroh Murakami ,  Yasushi Sasaki ,  Etsuo Yamamoto

    发明人： Yuhichiroh Murakami ,  Yasushi Sasaki ,  Etsuo Yamamoto

    IPC分类号： G05F3/16

    CPC分类号： G05F3/16 ,  G09G3/3674 ,  G09G2310/0286 ,  G09G2310/0291 ,  H04L25/0272

    摘要： A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal; and a resistor having (i) a first end connected to the output terminal and (ii) a second end connected to a second power source. This arrangement allows the signal processing circuit to maintain an output potential even after a bootstrap effect has worn off.

    摘要翻译： 本发明的信号处理电路包括：第一和第二输入端; 输出端子; 自举电容器; 与第二输入端子和输出端子连接的第一输出部分; 连接到第一输入端子的第二输出部分，第一电源和输出端子; 用于控制所述自举电容器的电荷的电荷控制部分，所述电荷控制部分连接到所述第一输入端子; 以及电阻器，其具有（i）连接到所述输出端子的第一端和（ii）连接到第二电源的第二端。 这种布置允许信号处理电路即使在自举效应已经磨损之后仍然保持输出电位。