Systems, devices, and methods for suppressing frequency spurs in mixers
    11.
    发明授权
    Systems, devices, and methods for suppressing frequency spurs in mixers 有权
    用于抑制混频器频率杂散的系统,设备和方法

    公开(公告)号:US08559905B2

    公开(公告)日:2013-10-15

    申请号:US11950831

    申请日:2007-12-05

    IPC分类号: H04B1/10 H04K3/00

    CPC分类号: H03D7/02

    摘要: Systems, devices and methods are disclosed for suppressing the 2LO frequency spur, output from a mixer. In various exemplary embodiments, a DC bias circuit is electrically connected to provide DC bias to one or more non-linear elements of the mixer. The biasing voltage is used to cause the current-voltage characteristics and/or junction capacitances between non-linear elements to be more symmetric and/or to suppress 2LO leakage currents that form 2LO frequency spurs at the output of the mixer. The non-linear elements may comprise one of: BJT's, diodes, and FET's. The mixer may be one of: a subharmonic mixer; a fundamental resistive mixer; a fundamental subharmonic transconductance mixer; and a fundamental transconductance mixer comprising an anti-parallel diode pair. The system may further be configured to automatically determine an appropriate DC bias voltage level that will improve one of the LO-IF isolation and the LO-RF isolation.

    摘要翻译: 公开了用于抑制从混频器输出的2LO频率支线的系统,装置和方法。 在各种示例性实施例中,DC偏置电路电连接以向混频器的一个或多个非线性元件提供DC偏置。 偏置电压用于使非线性元件之间的电流 - 电压特性和/或结电容更为对称和/或抑制在混频器输出端形成2LO频率杂散的2LO漏电流。 非线性元件可以包括以下之一:BJT,二极管和FET。 混合器可以是以下之一:次谐波混合器; 基本电阻混频器; 一种基本的次谐波跨导混频器; 以及包括反并联二极管对的基本跨导混频器。 该系统还可以被配置为自动确定将改善LO-IF隔离和LO-RF隔离之一的适当DC偏置电压电平。

    Active Phased Array Architecture
    12.
    发明申请
    Active Phased Array Architecture 有权
    有源相控阵列架构

    公开(公告)号:US20120299775A1

    公开(公告)日:2012-11-29

    申请号:US13540394

    申请日:2012-07-02

    IPC分类号: H01Q3/00

    摘要: In an exemplary embodiment, a phased array solid-state architecture has dual-polarized feeds and is manufactured, for example, on highly flexible silicon germanium (SiGe). The implementation of dual-polarized feeds facilitates the operation of phased arrays where the polarization can be statically or dynamically controlled on a subarray or element basis. In an exemplary embodiment, the sub-component control is configured to optimize a performance characteristic associated with polarization, such as phase or amplitude adjustment. An active phased array architecture may replace traditional distributed and GaAs implementations for the necessary functions required to operate electronically steerable phased array antennas. The architecture combines active versions of vector generators, power splitters, power combiners, and RF hybrids in a novel fashion to realize a fully or substantially monolithic solution for a wide range of antenna applications that can be realized with radiating elements having single-polarized or dual-polarized feeds,

    摘要翻译: 在示例性实施例中,相控阵列固态架构具有双极化馈电,并且例如在高度柔性的硅锗(SiGe)上制造。 双极化馈电的实现有助于相位阵列的操作,其中极化可以基于子阵列或元件静态或动态地控制。 在示例性实施例中,子部件控制被配置为优化与偏振相关联的性能特性,例如相位或幅度调整。 有源相控阵架构可以代替传统的分布式和GaAs实现,用于操作电子可控相控阵列天线所需的必要功能。 该架构以新颖的方式结合了矢量发生器,功率分配器,功率组合器和RF混合器的主动版本,以实现可以通过具有单极化或双重放大单元的辐射元件实现的宽范围天线应用的完全或基本上单片解决方案 极化饲料,

    LEADFRAME PACKAGE WITH INTEGRATED PARTIAL WAVEGUIDE INTERFACE
    13.
    发明申请
    LEADFRAME PACKAGE WITH INTEGRATED PARTIAL WAVEGUIDE INTERFACE 有权
    具有集成的部分波导接口的LEADFRAME封装

    公开(公告)号:US20120051000A1

    公开(公告)日:2012-03-01

    申请号:US13221693

    申请日:2011-08-30

    IPC分类号: H05K1/14 H01L31/18

    摘要: A MMIC package is disclosed comprising: a leadframe based overmolded package, a die positioned within the overmolded package; and a partial waveguide interface, wherein the partial waveguide interface is integral with the overmolded package facilitating low cost and reliable assembly. Also disclosed is an overmolded package where the die sits on a metal portion exposed on the bottom of the package and the package is configured for attachment to a chassis of a transceiver such that heat from the die is easily dissipated to the chassis with a direct thermal path. The disclosure facilitates parallel assembly of MMIC packages and use of pick and place/surface mounting technology for attaching the MMIC packages to the chassis of transceivers. This facilitates reliable and low cost transceivers.

    摘要翻译: 公开了一种MMIC封装,包括:基于引线框的包覆成型封装,位于所述包覆成型封装内的管芯; 和部分波导接口,其中部分波导接口与包覆成型的封装集成,促进了低成本和可靠的组装。 还公开了一种包覆成型的封装,其中管芯位于暴露在封装底部的金属部分上,并且封装构造成用于附接到收发器的底架,使得来自模具的热量容易地以直接热量散发到底架 路径。 本公开有助于MMIC封装的并行组装以及使用拾取和放置/表面安装技术将MMIC封装连接到收发器的底盘。 这有助于可靠和低成本的收发器。

    Single oscillator transceiver
    14.
    发明授权
    Single oscillator transceiver 有权
    单振荡收发器

    公开(公告)号:US08116359B2

    公开(公告)日:2012-02-14

    申请号:US12961211

    申请日:2010-12-06

    IPC分类号: H04L5/16 H04B1/38

    CPC分类号: H04B1/408 H04B1/403

    摘要: A frequency plan is provided for particular use in a transceiver. Advantageously, a single oscillator may be used to generate desired frequency signals. One or more power splitters receive the signal and equally divide the signal into first and second signals having a frequency substantially equal to the original. Multipliers on each arm of the transceiver receive a signal and increase the frequency of the signal. In one exemplary embodiment, multiple signals having different frequencies may be transmitted over the same cable due in part to the generated frequency separation between the signals. In another exemplary embodiment, multiple signals may be transmitted over multiple cables. Additionally, multiple signals over one or more cables may be transmitted at or below 3 GHz.

    摘要翻译: 提供频率计划用于收发器中的特定用途。 有利地,可以使用单个振荡器来产生期望的频率信号。 一个或多个功率分配器接收信号并且将信号等分成具有基本上等于原始频率的频率的第一和第二信号。 收发器的每个臂上的乘数接收信号并增加信号的频率。 在一个示例性实施例中,具有不同频率的多个信号可以通过相同的电缆传输,部分是由于信号之间产生的频率间隔。 在另一示例性实施例中,多个信号可以通过多个电缆传输。 此外,一根或多根电缆上的多个信号可以在3 GHz或以下传输。

    PROGRAMMABLE RF ARRAY
    15.
    发明申请
    PROGRAMMABLE RF ARRAY 有权
    可编程RF阵列

    公开(公告)号:US20110102074A1

    公开(公告)日:2011-05-05

    申请号:US12917325

    申请日:2010-11-01

    申请人: Kenneth V. Buer

    发明人: Kenneth V. Buer

    IPC分类号: H01L25/00

    摘要: The present disclosure relates to radio frequency integrated circuits. More particularly, systems, devices and methods related to field programmable, software implemented, radio frequency integrated circuits are disclosed. In accordance with an exemplary embodiment, a field programmable, software implemented, radio frequency integrated circuit may comprise a high frequency IF embodiment. An input signal may be up converted to a high frequency, such as 60 GHz. Next, the amplitude and/or phase may be adjusted as desired. Subsequently, the signal may be down converted.

    摘要翻译: 本公开涉及射频集成电路。 更具体地,公开了与现场可编程,软件实现的射频集成电路相关的系统,设备和方法。 根据示例性实施例,现场可编程,软件实现的射频集成电路可以包括高频IF实施例。 输入信号可以被上变频到高频,例如60GHz。 接下来,可以根据需要调整振幅和/或相位。 随后,信号可能被下变频。

    Phase shifter with flexible control voltage

    公开(公告)号:US07843282B2

    公开(公告)日:2010-11-30

    申请号:US12467945

    申请日:2009-05-18

    IPC分类号: H01P1/18

    CPC分类号: H03H11/20 H03H7/20

    摘要: The invention provides a phase shifter with flexible control voltage that is useful with all RF systems that phase shift a RF signal. The phase shifter according to the present invention may comprise transistors used as switching elements. In one aspect, the phase shifter provides the option of controlling a phase shifter with either a positive or a negative voltage control signal. For example, the dc ground of the transistors included in the phase shifter may be floated, either fixed or adjusted. The RF grounding of the transistors may be achieved by in-band resonant capacitors. Thus, the control voltage provided to the transistors is flexible in that it may be connected to a positive or negative control voltage, or it may be connected to ground, or it may swing from a positive control voltage to a negative control voltage or vice versa.

    SINGLE OSCILLATOR TRANSCEIVER
    17.
    发明申请
    SINGLE OSCILLATOR TRANSCEIVER 有权
    单振荡器收发器

    公开(公告)号:US20100112961A1

    公开(公告)日:2010-05-06

    申请号:US12614288

    申请日:2009-11-06

    IPC分类号: H04B1/40

    CPC分类号: H04B1/408

    摘要: A frequency plan is provided for particular use in a transceiver. Advantageously, a single oscillator may be used to generate desired frequency signals. One or more power splitters receive the signal and equally divide the signal into first and second signals having a frequency substantially equal to the original. Multipliers on each arm of the transceiver receive a signal and increase the frequency of the signal. In one exemplary embodiment, multiple signals having different frequencies may be transmitted over the same cable due in part to the generated frequency separation between the signals. In another exemplary embodiment, multiple signals may be transmitted over multiple cables. In another exemplary embodiment, the frequency plan may self correct a transmit signal based on a reference signal, such as the receive signal. Additionally, multiple signals over one or more cables may be transmitted at or below 3 GHz.

    摘要翻译: 提供频率计划用于收发器中的特定用途。 有利地,可以使用单个振荡器来产生期望的频率信号。 一个或多个功率分配器接收信号并且将信号等分成具有基本上等于原始频率的频率的第一和第二信号。 收发器的每个臂上的乘数接收信号并增加信号的频率。 在一个示例性实施例中,具有不同频率的多个信号可以通过相同的电缆传输,部分是由于信号之间产生的频率间隔。 在另一示例性实施例中,多个信号可以通过多个电缆传输。 在另一示例性实施例中,频率计划可以基于诸如接收信号的参考信号来自发校正发射信号。 此外,一根或多根电缆上的多个信号可以在3 GHz或以下传输。

    POWER EFFICIENT MULTISTAGE AMPLIFIER AND DESIGN METHOD
    19.
    发明申请
    POWER EFFICIENT MULTISTAGE AMPLIFIER AND DESIGN METHOD 有权
    功率有效的多功能放大器和设计方法

    公开(公告)号:US20080231374A1

    公开(公告)日:2008-09-25

    申请号:US11688729

    申请日:2007-03-20

    IPC分类号: H03F3/68

    CPC分类号: H03F3/189 H03F1/02

    摘要: A multistage amplifier and design method are disclosed. The multistage amplifier has a plurality of amplifier stages, each stage having an amplifier designed and biased to operate at or near the amplifier's power added efficiency (PAE) peak. The PAE peak of each of the amplifier is at or near the amplifiers linear-compression transition region, providing a multistage power amplifier that is power efficient and has desirable amplitude to amplitude and amplitude to phase power transfer characteristics. The amplifier is designed by matching the output impedance of a final stage with a load. Amplifier stages are iteratively designed from the last stage to the first. At each stage, an amplifier and drive circuit are designed. The drive circuit and amplifier are designed to provide each stage with output impedance matched to the input impedance of the following stage and to operate at or near the PAE peak of the amplifier.

    摘要翻译: 公开了一种多级放大器和设计方法。 多级放大器具有多个放大器级,每级具有设计和偏置以在放大器的功率增加效率(PAE)峰值附近操作的放大器。 每个放大器的PAE峰值处于或靠近放大器线性压缩过渡区域,提供功率有效的多级功率放大器,并具有期望的振幅和幅度与相位功率传输特性。 放大器的设计是通过匹配最后一级的输出阻抗与负载。 从最后阶段到第一阶段迭代设计放大器级。 在每个阶段,设计放大器和驱动电路。 驱动电路和放大器被设计成为每个级提供与下一级的输入阻抗匹配的输出阻抗,并在放大器的PAE峰值处或附近工作。

    Direct contact semiconductor cooling
    20.
    发明授权
    Direct contact semiconductor cooling 有权
    直接接触半导体冷却

    公开(公告)号:US07157793B2

    公开(公告)日:2007-01-02

    申请号:US10849097

    申请日:2004-05-19

    IPC分类号: H01L23/34 G01R31/26

    摘要: Thermal spreading resistance, associated with small geometry electronic features that generate heat on a semiconductor, may be reduced through the addition of a thermally conductive fluid. For example, a dielectric fluid may be used within a volume between a semiconductor package and the semiconductor substrate. Therefore, direct thermal cooling may be employed to reduce the thermal spreading resistance often encountered in MMIC power amplifier devices. Furthermore, exemplary methods to achieve this sealing are described herein.

    摘要翻译: 通过添加导热流体可以减少与在半导体上产生热量的小几何电子特征相关联的热扩散阻力。 例如,可以在半导体封装和半导体衬底之间的体积内使用电介质流体。 因此,可以采用直接热冷却来降低MMIC功率放大器器件中经常遇到的耐热扩散电阻。 此外,本文描述了实现该密封的示例性方法。