公开(公告)号：US07183142B2

公开(公告)日：2007-02-27

申请号：US10905615

申请日：2005-01-13

申请人： Brent A. Anderson ,  Kerry Bernstein ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Kerry Bernstein ,  Edward J. Nowak

IPC分类号： H01L21/335

CPC分类号： H01L29/785 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66795

摘要： A method of manufacturing fin-type field effect transistors (FinFETs) forms a silicon layer above a substrate, forms a mask pattern above the silicon layer using a multi-step mask formation process, patterns the silicon layer into silicon fins using the mask pattern such that the silicon fins only remain below the mask pattern, removes the mask pattern to leave the fins on the substrate, and forms gate conductors over the fins at a non-perpendicular angle to the fins.

摘要翻译： 制造鳍型场效应晶体管（FinFET）的方法在衬底上形成硅层，使用多步骤掩模形成工艺在硅层上形成掩模图案，使用掩模图案将硅层图案化为硅散热片 硅片仅保留在掩模图案之下，去除掩模图案以将散热片留在基板上，并且以与散热片非垂直的角度在翅片上形成栅极导体。

公开(公告)号：US06577178B1

公开(公告)日：2003-06-10

申请号：US10064504

申请日：2002-07-23

申请人： Kerry Bernstein ,  Peter E. Cottrell ,  Edward J. Nowak ,  Norman J. Rohrer ,  Douglas W. Stout

发明人： Kerry Bernstein ,  Peter E. Cottrell ,  Edward J. Nowak ,  Norman J. Rohrer ,  Douglas W. Stout

IPC分类号： H03K1730

CPC分类号： H03K19/00361 ,  H03K19/0948

摘要： A circuit includes a resistance-capacitance (RC) structure connected to a first set of transistors and a second set of transistors that perform the same logical function as the first set of transistors. The first set of transistors have thinner gate oxides than the second set of transistors. The RC structure drains an electric field from the first set of transistors, such that the first set of transistors are on only during initial transistor switching. In other words, the RC structure turns off the first set of transistors after transistor switching is completed. Also, the first set of transistors and the second set of transistors share common inputs and outputs. The first set of transistors exhibit higher tunneling currents than the second set of transistors. The thinner gate oxides of the first set of transistors cause the first set of transistors to exhibit higher device currents than the second set of transistors. The RC structure includes a capacitor connected to a gate of the first set of transistors and a resistor connected to the capacitor and to ground.

摘要翻译： 电路包括连接到第一组晶体管的电阻 - 电容（RC）结构和执行与第一组晶体管相同的逻辑功能的第二组晶体管。 第一组晶体管具有比第二组晶体管更薄的栅极氧化物。 RC结构从第一组晶体管引出电场，使得第一组晶体管仅在初始晶体管切换期间导通。 换句话说，在晶体管切换完成之后，RC结构关闭第一组晶体管。 此外，第一组晶体管和第二组晶体管共享公共输入和输出。 第一组晶体管表现出比第二组晶体管更高的隧穿电流。 第一组晶体管的较薄的栅极氧化物导致第一组晶体管表现出比第二组晶体管更高的器件电流。 RC结构包括连接到第一组晶体管的栅极的电容器和连接到电容器并接地的电阻器。

公开(公告)号：US06191628B1

公开(公告)日：2001-02-20

申请号：US09224763

申请日：1999-01-04

申请人： Kerry Bernstein ,  Edward J. Nowak ,  Norman J. Rohrer

发明人： Kerry Bernstein ,  Edward J. Nowak ,  Norman J. Rohrer

IPC分类号： H03K512

CPC分类号： H03K19/00323 ,  H03K5/131 ,  H03K5/133 ,  H03K19/00361 ,  H03K2005/00071

摘要： A circuit for selectively controlling the slew rate of a signal on a data line. A capacitor is connected at one end to a common terminal of a power supply and to a switching circuit. The switching circuit advantageously connects the capacitor to the data line in response to a control pulse, capacitively loading the data line so that slew rate is decreased. When the control pulse assumes a different state, the capacitor is connected by the switching circuit to a terminal of a power supply, and acts as a decoupling capacitor. The dual role of the capacitor provides for efficient circuit layout by utilizing one component in two functions.

摘要翻译： 用于选择性地控制数据线上的信号的转换速率的电路。 电容器一端连接到电源的公共端子和开关电路。 开关电路有利地将电容器响应于控制脉冲连接到数据线，电容性地加载数据线，使得转换速率降低。 当控制脉冲处于不同状态时，电容器通过开关电路连接到电源的端子，并用作去耦电容器。 电容器的双重作用通过利用两个功能中的一个组件来提供有效的电路布局。

公开(公告)号：US09368410B2

公开(公告)日：2016-06-14

申请号：US12033280

申请日：2008-02-19

申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Edmund J. Sprogis

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Edmund J. Sprogis

IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/76205 ,  H01L21/823878 ,  H01L29/7846

摘要： A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.

摘要翻译： 公开了一种半导体器件和制造方法，其具有施加到其上的拉伸和/或压缩应变。 该方法包括在材料中形成至少一个沟槽; 以及通过氧化工艺填充所述至少一个沟槽，从而在器件的通道中形成应变集中。 该结构包括分别在第一通道上具有沟道和第一氧化沟槽的栅极结构。 第一氧化沟槽在通道中产生应变分量以增加器件性能。

公开(公告)号：US08866226B2

公开(公告)日：2014-10-21

申请号：US13345871

申请日：2012-01-09

申请人： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

发明人： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/762

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L27/1203

摘要： At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.

摘要翻译： 至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。 浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。 所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。 感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。

公开(公告)号：US08673683B2

公开(公告)日：2014-03-18

申请号：US13492131

申请日：2012-06-08

申请人： James W. Adkisson ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Molly J. Leitch ,  Edward J. Nowak

发明人： James W. Adkisson ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Molly J. Leitch ,  Edward J. Nowak

IPC分类号： H01L51/40 ,  H01L21/8232 ,  H01L21/336

CPC分类号： H01L29/1606 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/186 ,  H01L27/1222 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66045 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78684 ,  H01L29/78696

摘要： Manufacturing a semiconductor structure including: forming a seed material on an insulator layer; forming a graphene field effect transistor (FET) on the seed material; and forming an air gap under the graphene FET by removing the seed material.

摘要翻译： 制造半导体结构，包括：在绝缘体层上形成种子材料; 在种子材料上形成石墨烯场效应晶体管（FET）; 并通过除去种子材料在石墨烯FET下方形成气隙。

公开(公告)号：US08617412B2

公开(公告)日：2013-12-31

申请号：US12966370

申请日：2010-12-13

申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Jeffrey W. Sleight

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Jeffrey W. Sleight

IPC分类号： C23F3/00 ,  B01D29/46 ,  H01L21/02

CPC分类号： B01D39/2082 ,  B01D2239/025 ,  B01D2239/0613 ,  B01D2239/10 ,  B01D2239/1233 ,  B82Y30/00

摘要： The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires.

摘要翻译： 本公开一般涉及纳米过滤器及其形成方法，以及过滤方法。 纳米过滤器包括基底和位于入口和出口之间的至少一个纳米线结构。 纳米线结构可以包括多个垂直堆叠的水平纳米线。

公开(公告)号：US08609453B2

公开(公告)日：2013-12-17

申请号：US12951601

申请日：2010-11-22

申请人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21/00

CPC分类号： H01L31/186 ,  H01L31/0248 ,  H01L31/068 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A reusable substrate and method for forming single crystal silicon solar cells are described. A method of forming a photovoltaic cell includes forming an intermediate layer on a monocrystalline silicon substrate, forming a monocrystalline silicon layer on the intermediate layer, and forming electrical features in the monocrystalline silicon layer. The method further includes forming openings in the monocrystalline silicon layer, and detaching the monocrystalline silicon layer from the substrate by selectively etching the intermediate layer through the openings.

摘要翻译： 描述了可重复使用的基板和用于形成单晶硅太阳能电池的方法。 形成光伏电池的方法包括在单晶硅衬底上形成中间层，在中间层上形成单晶硅层，并在单晶硅层中形成电特征。 该方法还包括在单晶硅层中形成开口，并且通过选择性地通过开口蚀刻中间层，从而将单晶硅层从衬底上分离出来。

公开(公告)号：US20130240997A1

公开(公告)日：2013-09-19

申请号：US13424319

申请日：2012-03-19

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

IPC分类号： H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L27/1104 ,  H01L29/7843

摘要： Solutions for forming stress optimizing contact bars and contacts are disclosed. In one aspect, a semiconductor device is disclosed including an n-type field effect transistor (NFET) having source/drain regions; a p-type field effect transistor (PFET) having source/drain regions; a stress inducing layer over both the NFET and the PFET, the stress inducing layer inducing only one of a compressive stress and a tensile stress; a contact bar extending through the stress inducing layer and coupled to at least one of the source/drain regions of a selected device of the PFET and the NFET to modify a stress induced in the selected device compared to a stress induced in the other device; and a round contact extending through the stress inducing layer and coupled to at least one of the source/drain regions of the other device of the PFET and the NFET.

摘要翻译： 公开了用于形成应力优化接触棒和触点的解决方案。 一方面，公开了一种具有源极/漏极区域的n型场效应晶体管（NFET）的半导体器件; 具有源极/漏极区域的p型场效应晶体管（PFET） 在NFET和PFET两者上的应力诱导层，应力诱导层仅引起压缩应力和拉伸应力之一; 接触棒延伸穿过应力感应层并且耦合到PFET和NFET的所选器件的源/漏区中的至少一个，以修改与在另一器件中感应的应力相比在所选器件中感应的应力; 以及延伸穿过应力感应层并且耦合到PFET和NFET的另一个器件的源极/漏极区域中的至少一个的圆形接触。

公开(公告)号：US08492823B2

公开(公告)日：2013-07-23

申请号：US12473627

申请日：2009-05-28

申请人： Edward J. Nowak

发明人： Edward J. Nowak

IPC分类号： H01L29/94 ,  H01L29/93 ,  H01L27/08 ,  H01L21/329

CPC分类号： H01L29/93 ,  H01L29/66174

摘要： Disclosed is a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. The fabrication of semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode.