利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

36 条记录 (耗时 0.033 秒)

    SiC MOSFETS AND SELF-ALIGNED FABRICATION METHODS THEREOF
    12.
    发明申请
    SiC MOSFETS AND SELF-ALIGNED FABRICATION METHODS THEREOF 有权
    SiC MOSFET和自对准的制造方法

    公开(公告)号：US20090242901A1

    公开(公告)日：2009-10-01

    申请号：US12483469

    申请日：2009-06-12

    申请人： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

    发明人： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

    IPC分类号： H01L29/24 ,  H01L21/285 ,  H01L29/772

    CPC分类号： H01L29/4975 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/872

    摘要： The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.

    摘要翻译： 本发明提供一种制造金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：在碳化硅层上形成源极区域并退火源极区域。 在源区和碳化硅层上形成栅氧化层。 该方法还包括在栅极氧化物层上设置栅电极，并在栅电极和栅极氧化物层上设置电介质层。 该方法还包括蚀刻介电层的一部分和栅极氧化物层的一部分以在栅电极上形成侧壁。 金属层设置在栅电极，侧壁和源极区上。 该方法还包括通过使金属层经受至少约800℃的温度来形成栅极接触和源极接触。栅极接触和源极接触包括金属硅化物。 栅极触点与源极之间的距离小于0.6μm。 还提供了一个垂直的SiC MOSFET。

    SiC MOSFETs and self-aligned fabrication methods thereof
    14.
    发明授权
    SiC MOSFETs and self-aligned fabrication methods thereof 有权
    SiC MOSFET及其自对准制造方法

    公开(公告)号：US08377812B2

    公开(公告)日：2013-02-19

    申请号：US12483469

    申请日：2009-06-12

    申请人： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

    发明人： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

    IPC分类号： H01L21/28

    CPC分类号： H01L29/4975 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/872

    摘要： The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.

    摘要翻译： 本发明提供一种制造金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：在碳化硅层上形成源极区域并退火源极区域。 在源区和碳化硅层上形成栅氧化层。 该方法还包括在栅极氧化物层上设置栅电极，并在栅电极和栅极氧化物层上设置电介质层。 该方法还包括蚀刻介电层的一部分和栅极氧化物层的一部分以在栅电极上形成侧壁。 金属层设置在栅电极，侧壁和源极区上。 该方法还包括通过使金属层经受至少约800℃的温度来形成栅极接触和源极接触。栅极接触和源极接触包括金属硅化物。 栅极接触点和源极接触点之间的距离小于约0.6μm。 还提供了一个垂直的SiC MOSFET。