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    MEMORY SYSTEM, SEMICONDUCTOR STORAGE DEVICE, AND METHOD FOR READING OUT DATA
    12.
    发明申请
    MEMORY SYSTEM, SEMICONDUCTOR STORAGE DEVICE, AND METHOD FOR READING OUT DATA 有权

    公开(公告)号：US20220083261A1

    公开(公告)日：2022-03-17

    申请号：US17335511

    申请日：2021-06-01

    Applicant: Kioxia Corporation

    Inventor： Daisuke FUJIWARA ,  Tomoya SANUKI ,  Toshio FUJISAWA

    IPC: G06F3/06

    Abstract: A memory system of an embodiment includes a NAND memory and a memory controller. The NAND memory includes an encoder configured to convert first data into second data including a plurality of code words generated by dividing the first data into the code words, generate parity data in a horizontal direction of the second data for error check and correct for each code word and encode the first data, and a decoder. A control circuit of the NAND memory controls the decoder to perform hard decision decoding using the parity data in the horizontal direction on readout target data when a readout command is received and outputs the decoded readout target data to the memory controller when the hard decision decoding of the readout target data is successful.

    MEMORY SYSTEM
    13.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20220011963A1

    公开(公告)日：2022-01-13

    申请号：US17197667

    申请日：2021-03-10

    Applicant: Kioxia Corporation

    Inventor： Tomoya SANUKI ,  Yuta AIBA ,  Hitomi TANAKA ,  Masayuki MIURA ,  Mie MATSUO ,  Toshio FUJISAWA ,  Takashi MAEDA

    IPC: G06F3/06

    Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of −40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of −40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.

    SEMICONDUCTOR MEMORY DEVICE
    14.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210082879A1

    公开(公告)日：2021-03-18

    申请号：US16806079

    申请日：2020-03-02

    Applicant: Kioxia Corporation

    Inventor： Tomoya SANUKI ,  Hiroshi MAEJIMA ,  Tetsuaki UTSUMI

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.

    CONTROLLER AND CONTROL METHOD
    16.
    发明公开
    CONTROLLER AND CONTROL METHOD 审中-公开

    公开(公告)号：US20240126479A1

    公开(公告)日：2024-04-18

    申请号：US18483468

    申请日：2023-10-09

    Applicant: Kioxia Corporation

    Inventor： Yoshihiro OHBA ,  Tomoya SANUKI ,  Takeshi ISHIHARA

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0679

    Abstract: According to one embodiment, a controller includes a first interface, a second interface, a virtual register table, a memory management unit and a calculation processing unit. The first interface receives an I/O command from a host. The second interface transmits and receives first host data to and from a storage. The virtual register table has a virtual address specified by a page number assigned to a page in which data to be used to process a calculation instruction is stored and a page offset, and a data size of the data. The memory management unit stores, into a memory, the copy of the first host data, and updates the virtual register table. The calculation processing unit processes the calculation instruction by referring to the virtual register table.

    RADIATION DETECTION DEVICE, SEMICONDUCTOR MEMORY DEVICE AND RADIATION DETECTION METHOD
    17.
    发明申请
    RADIATION DETECTION DEVICE, SEMICONDUCTOR MEMORY DEVICE AND RADIATION DETECTION METHOD 有权

    公开(公告)号：US20230060583A1

    公开(公告)日：2023-03-02

    申请号：US17666463

    申请日：2022-02-07

    Applicant: KIOXIA CORPORATION

    Inventor： Tomoya SANUKI

    IPC: G01T1/24 ,  G01T7/00

    Abstract: A radiation detection device includes a non-volatile memory chip including a plurality of stacked memory cells, and a controller configured to detect gamma rays incident on the non-volatile memory chip during a gamma ray detection window according to a data inversion or a threshold voltage change of at least some of the memory cells in the non-volatile memory chip during the gamma ray detection window.

    SEMICONDUCTOR STORAGE DEVICE AND SYSTEM
    18.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE AND SYSTEM 有权

    公开(公告)号：US20230017909A1

    公开(公告)日：2023-01-19

    申请号：US17681547

    申请日：2022-02-25

    Applicant: KIOXIA CORPORATION

    Inventor： Tomoya SANUKI ,  Keisuke NAKATSUKA ,  Daisuke FUJIWARA ,  Toshio FUJISAWA

    IPC: G11C11/4096 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4097

    Abstract: A semiconductor storage device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory strings, a plurality of word lines, each of which is connected to the memory strings, and a plurality of bit lines connected to the memory strings, respectively. The plurality of bit lines are grouped into a plurality of bit line groups. The control circuit is configured to receive a read command and first address information specifying one or more of the bit line groups. The control circuit is configured to, in response to the read command, read data selectively from each memory string connected to each bit line in the one or more bit line groups specified by the first address information, and output the read data.

    SEMICONDUCTOR MEMORY DEVICE
    20.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220130754A1

    公开(公告)日：2022-04-28

    申请号：US17438728

    申请日：2019-03-19

    Applicant: Kioxia Corporation

    Inventor： Keisuke NAKATSUKA ,  Yasuhito YOSHIMIZU ,  Tomoya SANUKI ,  Fumitaka ARAI

    IPC: H01L23/522 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A semiconductor memory device including: plural first conductive layers stacked on a substrate; plural second conductive layers each stacked between the first conductive layers; a pillar that extends in a stacking direction of the first and second conductive layers and forms plural memory cells at intersections of the first and second conductive layers in a region where first and second conductive layers are arranged; a first contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the first conductive layers in the region where the first and second conductive layers are arranged; and a second contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the second conductive layers in the region where the first conductive layers and second conductive layers are arranged.

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