公开(公告)号：US11329157B2

公开(公告)日：2022-05-10

申请号：US16607410

申请日：2019-08-20

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Jun Woo Son ,  Jae Hur

IPC: H01L21/00 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3205 ,  H01L27/108 ,  H01L29/861

Abstract: A two-terminal biristor in which a polysilicon emitter layer is inserted and a method of manufacturing the same are provided. The method of manufacturing the two-terminal biristor according to an embodiment of the present disclosure includes forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, forming a third semiconductor layer of the first type on the second semiconductor layer, and forming a polysilicon layer of the first type on the third semiconductor layer.

公开(公告)号：US11322613B2

公开(公告)日：2022-05-03

申请号：US16896346

申请日：2020-06-09

Applicant: Korea Advanced Institute Of Science And Technology

Inventor： Yang-Kyu Choi ,  Joonkyu Han

IPC: H01L29/78 ,  H01L27/108 ,  H01L29/06 ,  G06N3/04 ,  H01L29/45 ,  G06N3/063 ,  H01L29/08

Abstract: A structure and an operation of a transistor, which is a vertical transistor in which a nanowire-type floating body layer is vertically formed or a horizontal transistor in which a floating body layer is horizontally formed, and implements a spike operation of a neuron by storing and releasing charges inside the transistor, and a neuromorphic system using the same are provided. The vertical transistor includes a floating body layer in a form of a vertical nanowire vertically formed on a substrate, a source and a drain formed above and below the floating body layer, a gate insulating layer formed on the source and surrounding the floating body layer, a gate formed outside the gate insulating layer, and a contact metal being in contact with the source, the drain and the gate to input or output an electrical signal.

公开(公告)号：US20210391462A1

公开(公告)日：2021-12-16

申请号：US17346372

申请日：2021-06-14

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Joon-Kyu Han

IPC: H01L29/78 ,  H01L29/45 ,  G06N3/063

Abstract: Disclosed is a single transistor with a double gate structure for an adjustable firing threshold voltage and a neuromorphic system using the same. A single transistor neuron with a double gate structure according to an example embodiment includes a barrier material layer formed on a semiconductor substrate and comprising a hole barrier material or an electron barrier material; a floating body layer formed on the barrier material layer; a source and a drain formed at both sides of the floating body layer, respectively; a driving gate formed at a first side of the floating body layer without contacting the source and the drain; a control gate formed at a second side of the floating body layer without contacting the source and the drain; and a gate insulating film formed between the floating body layer and the driving gate and between the floating body layer and the control gate.

公开(公告)号：US10665671B2

公开(公告)日：2020-05-26

申请号：US15428727

申请日：2017-02-09

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Byung-Hyun Lee ,  Min-Ho Kang

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/265 ,  H01L21/324 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78

Abstract: Disclosed is a method of manufacturing a junctionless transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels is exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels which is exposed though the hole.

公开(公告)号：US20190393237A1

公开(公告)日：2019-12-26

申请号：US16175480

申请日：2018-10-30

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Jun-Young Park

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/367 ,  H01L23/373

Abstract: Disclosed are a vertically-integrated 3-dimensional flash memory for improving a reliability of cells and a fabrication method thereof. The fabrication method of the vertically-integrated 3-dimensional flash memory includes sequentially stacking a first insulating layer and a second insulating layer on a substrate to form a plurality of insulating layers, etching a portion of the insulating layers to expose an area of the substrate, forming a channel layer on a side surface of the etched insulating layers and on the substrate, forming a first macaroni layer on the channel layer, and forming a second macaroni layer on the first macaroni layer such that a side surface and a lower surface of the second macaroni layer are surrounded by the first macaroni layer.

公开(公告)号：US10084128B2

公开(公告)日：2018-09-25

申请号：US15426719

申请日：2017-02-07

Applicant: Korea Advanced Institute of Science And Technology ,  CENTER FOR INTEGRATED SMART SENSORS FOUNDATION

Inventor： Yang-Kyu Choi ,  Jun-Young Park ,  Chang-Hoon Jeon

IPC: H01L29/06 ,  H03H9/24 ,  H01L29/775 ,  H01L21/762 ,  H01L27/088 ,  G11C16/04 ,  H01L27/11 ,  H01L21/74 ,  H01L29/78 ,  H01L29/792 ,  H01L45/00 ,  H01L29/423 ,  H03K17/687

CPC classification number: H01L45/1206 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L45/1226 ,  H03K17/687

Abstract: Provided is a method for increasing a driving current of a junctionless transistor that includes: a substrate; a source region and a drain region which are formed on the substrate and are doped with the same type of dopant; a nanowire channel region which connects the source region and the drain source and is doped with the same type dopant as that of the source region and the drain region; a gate insulation layer which is formed to surround the nanowire channel region; and a gate electrode which is formed on the gate insulation layer and is formed to surround the nanowire channel region. An amount of current flowing through the nanowire channel region is increased by joule heat generated by applying a voltage to the source region and the drain region.

公开(公告)号：US20180102477A1

公开(公告)日：2018-04-12

申请号：US15426719

申请日：2017-02-07

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Jun-Young Park ,  Chang-Hoon Jeon

IPC: H01L45/00 ,  H01L29/06 ,  H01L29/423 ,  H03K17/687

CPC classification number: H01L45/1206 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L35/00 ,  H01L45/1226 ,  H03K17/687

Abstract: Provided is a method for increasing a driving current of a junctionless transistor that includes: a substrate; a source region and a drain region which are formed on the substrate and are doped with the same type of dopant; a nanowire channel region which connects the source region and the drain source and is doped with the same type dopant as that of the source region and the drain region; a gate insulation layer which is formed to surround the nanowire channel region; and a gate electrode which is formed on the gate insulation layer and is formed to surround the nanowire channel region. An amount of current flowing through the nanowire channel region is increased by joule heat generated by applying a voltage to the source region and the drain region.